Practical Application to 1D Partial Runtime Reconfigurable Systems 56

The design method and guidelines, previously presented in this Chapter, have been used for building three runtime reconfigurable systems. Two of them are one dimensional virtual architectures that use bus communication and are described in this section, while the third one is a NoC based reconfigurable system with a two dimensional virtual architecture that is the main topic of Chapter 3.

In order to design the reconfigurable systems, two general one dimensional slot distributions for two different Virtex II FPGA will be selected from Table 2.4. By selecting the slot distribution, the first four steps of the presented method are covered.

For the last step, related to the on-chip interconnection, all the knowledge present in the previous section will be used to design bus communication structures that occupy less area and have better performance than the state of the art, as it will be seen in the results section of this Chapter. Also, the designed reconfigurable systems have been tested in terms of stability during reconfiguration and hard core relocation (reliability and flexibility goals).

The first system, described next, is for an XC2V1000 FPGA and the second one, described afterwards, is for an XC2V3000.

2.4.4.1 Bus Based Reconfigurable System for an XC2V1000 FPGA (Bus-v1)

This system is a first approach to achieve hard core relocation and the integration of the on-chip communications in the smallest possible area.

As it has been mentioned, the first four steps of the method are common for an entire FPGA family and have already been presented in section 2.4.2. Here, a slot distribution will be selected and the last point of the method, related to the on-chip communication is described below.

The selected slot distribution from Table 2.4 for the target FPGA, XC2V1000, is the one composed of six slots of four CLB columns width. However, the two rightmost slots have been reserved for on-chip bus arbitration. The remaining four slots have been used for hard core allocation tests.

2.4 Virtual Architectures for Partial RunTime Reconfigurable Systems. Design Method 57

A piece of the designed bus communication structure can be seen in Figure 2.20. The on-chip bus communication has been based on long P2M interconnection (see Figure 2.20). For achieving resource integration and thus lower area overhead, the bus has been composed of two wires types, built by different FPGA resources: i) based on long BM-TBUFs, four bidirectional wires used as data lines have been implemented and ii) eight P2M unidirectional wires from the fixed area to slots using long CLB interconnections.

The total amount of connection wires is twelve; however the communication structure needs only a single FPGA row resulting in higher integration. Differently, if the same amount of interconnections were implemented only with TBUFs, three rows would be needed.

Access points are key elements that permit to use the on-chip communication structure and guarantee relocation. They are designed using vertical short P2P CLB macros that have been slightly modified (see Figure 2.20). The CLB on one side of the interconnection has been hooked to the communication structure wires. Additionally, the FPGA bottom IOBs has been connected to the communication structure for validation purposes (reliability test).

Bus Access Point

Bus testing access Slot Bottom Boundary

Pass Through CLBS

Figure 2.20: Bus communication structure for an XC2V1000 (Bus-v1) built by long CLBs and buffer based macros.

All the files needed for the virtual architecture definition: the system and hard core templates, the macro structure files and the user constraint files have been created.

On top of the communication structure, using the architecture template, a bus based synchronous protocol has been defined for testing purposes. The system test IOBs have been connected to a logic analyzer to check data transitions stability during reconfiguration and, a set of relocated (with the tools presented in Chapter 4) hard cores that constantly transmit data to the fixed FPGA area have been loaded consecutively in different slot positions. Initially a core that communicates with fixed area (on the FPGA right side) has been loaded in the leftmost slot resulting in data transmissions along all

58 2.4 Virtual Architectures for Partial RunTime Reconfigurable Systems. Design Method

the FPGA width. After that, relocated cores have been loaded in different intermediate slots. As a result, the reconfigurable systems have been validated in terms of stability of the on-chip communication during reconfiguration and in terms of flexibility, as relocation tests have been successful.

2.4.4.2 Bus Based Reconfigurable System for an XC2V3000 FPGA (Bus-v2)

This, second, testing reconfigurable system main goal is to check the scalability of the solution by targeting another bigger FPGA (XC2V3000), increasing the number of bus wires and adding long P2P wires to the bus. Also, the number of required pass-through CLBs is reduced, as well as the possibility of border crossing wires, compared to the previous, Bus-v1, system. Again, a slot distribution will be selected from Table 2.4 and the last point of the method is described next. A section of the Bus-v2 communication structure can be seen in Figure 2.21.

Access Points

Communication Structure

Slot Boundaries

IOB testing access

CLB based interconnections

TBUF based interconnections

Figure 2.21: Bus communication structure for an XC2V3000 (Bus-v2), built by long CLBs and buffer based macros.

The selected slot distribution from Table 2.4 for the target XC2V3000 FPGA is the one that has eight slots of 6 CLB columns width. Again, the two rightmost slots have been reserved for bus arbitration.

Differently from Bus-v1, here the designed communication infrastructure is composed of three connection types:

1. Sixteen signals based on TBUFs long P2M bidirectional interconnections used for data transfer.

2. Sixteen unidirectional long P2M CLB interconnection wires from the fixed area to slots.