virtual architecture design method originally proposed in Chapter 2 and the support tools presented in Chapter 3, have been arranged and will be originally presented along the applications section in Chapter 5.
1.6 Summary and thesis Objectives
Designing a complete reconfigurable system nowadays is not an easy task. The commercially available solutions are quite restrictive, complex to use and require specialized designers. This complexity starts from the basics of the reconfigurable systems design methods, the hardware infrastructure, goes through hard core design flows, and ends by the runtime reconfiguration control. New solutions in all these aspects, oriented to bring flexibility and scalability to the system and to provide end to end reconfigurability are required. The main approach to be followed in this thesis work is to divide the system design process from the hard core design, in order to design highly flexible and scalable reconfigurable systems. The general goal is to permit a reconfigurable device to consume a board set of hard cores on one side, and on the other side, to permit the design of hard cores without the need of knowing the reconfigurable system specifics. To achieve this, new solutions, related to system design method and tools, as well as system runtime control, will be provided along the thesis and it will be shown that the provided solutions lead to the design of more flexible and scalable reconfigurable systems compared to the state of the art.
The main, detailed, objectives of this thesis work are listed below:
1. To provide a solution to the design of virtual architectures for reconfigurable systems that might permit to: i) design one and two dimensional flexible systems that permit hard cores to be freely allocated along the defined architecture, ii) improve the use of the FPGA resources and iii) permit stable reconfiguration (the on-chip communications have to remain active during the hard core hot swapping process). These goals are the main subject of Chapter 2.
2. To extend the system reconfigurability and provide reconfiguration not only of the system cores, but also to the on-chip communications. In Chapter 3 a NoC-based architecture solution that covers this goal will be originally proposed, along with a set of reconfiguration methods and suitable design resources that include, among others, an original packet format and a router architecture approach.
3. To define a set of tools and design flows that will provide support to the system flexibility. On one hand, the main objective for the design tools is to target embedded systems in order to provide higher independence and permit the system to consume different hard cores. On the other hand, for the design flows, the main objective is to facilitate the reconfigurable system design process, reduce the need of expert designer and detailed knowledge of the target reconfigurable system architecture, while keeping the provided solutions as close as possible to existing commercial tools. This topic is targeted in Chapter 4.
4. To demonstrate the feasibility and flexibility of the provided solutions, several systems with a different flexibility level have been created and integrated in four
1.6 Summary and thesis Objectives 23
different application domains: i) to a remote reconfigurable sensor network node, ii) to an automatic and transparent remote reconfigurable client device integrated in a client-server environment, iii) to debug a reconfigurable system and iv) in a complete on-chip communication emulation framework. The diversity of the selected application domains, described in Chapter5, is a result of the search of possible ”killer application” domains of partial runtime reconfigurable systems.
At this point it is highly important to remark that the amount of groups working in the different subjects of the reconfigurable systems research topic is constantly increasing.
Nowadays, the competitiveness and the advances in this topic are impressive. While a few years ago, the research groups in this topic were mainly in Europe and in USA and it was relatively easy to track all the progresses, now there are a lot of contributions from all over the world, being very active Asia. Consequently, the amount of published work is much larger than the included along the thesis.
For being more precise, and due to the board of topics to be discussed along the thesis, there is a state of the art (introduction) and a results part in each Chapter (but the applications one). Along the introduction section, a few selected works will be described in detail and compared with the proposed solutions in the Chapters’ results section. The selected works for each Chapter’s state of the art have been, in most of the cases, the contemporary ones and the closest related to this thesis.
24 1.6 Summary and thesis Objectives
Chapter 2
Reconfigurable Systems for Commercial FPGAs
Architectures of partially reconfigurable systems. A method for designing Virtual Architectures for partial RunTime Reconfigurable Systems (pRTRSs) is originally proposed.
The basics of the flexibility and scalability of a reconfigurable system are defined by its virtual architecture, which defines how the FPGA resources are distributed in order to map the systems, and how the different regions are interconnected. This Chapter proposes a general method for Virtual Architectures (VAs) design, which is a thesis original contribution.
In the first part of the Chapter, section 2.2 and section 2.3, existing partially reconfigurable systems design solutions from the industry and the academic community are presented.
In the second part, section 2.4, the virtual architectures design method is extensively described and used to build several, general, reconfigurable systems for commercial FPGAs. Further, two one dimensional bus based reconfigurable systems are presented and compared with the state of the art at the end of the Chapter in the results section 2.5, outlying the advantages of the proposed method. Finally, conclusions can be found in section 2.6.
2.1 Introduction 27
2.1 Introduction
A time diagram of the research groups that will be included in this Chapter state of the art described in the next subsections can be found in Figure 2.1. The works included in the Figure and in this section are related to one dimensional (1D) runtime reconfigurable systems. It is worthy to highlight that the main part of the presented in this Chapter related work are focused on bus based one dimensional systems and has been published between 2003-2006. After that, a tendency to move to Networks on Chip (NoCs) and two dimensional (2D) reconfigurable systems can be noticed, as it will be explained in Chapter 3, where a similar time diagram will be presented and the state of the art part is focused on 2D systems.
Although, the method proposed along this Chapter is valid for both possible models (1D and 2D), for clearness this Chapter will extensively present the method along with a general application to commercial Xilinx FPGAs and a design of two 1D bus based reconfigurable systems that will be compared at the end of the Chapter with other 1D systems from the state of the art.
2007 Year 2003 2005
2001
Lockwood-Horta et al.
1D P2P (Virtex) relocation
Hübner-Becker et al.
U. Karlsruhe 1D Bus (Virtex)
ESM U. Erlangen Nuremberg
1D Virtex II
Pazner-Walder et al.
Zurich – ETH 1D Bus Virtex II
Proposal Bus 1D, 2D relocation and high flexibility
(Virtex II/Pro) Moraes-Calazans et al.
1D Bus (Virtex) IMEC NoC 1D Virtex II
Modular Design Xilinx 1D all FPGA
Figure 2.1:One dimensional partially reconfigurable systems evolution time diagram.