Potential for fully reversible operations

The majority of “adiabatic” logic families mentioned in Chapter 2 are in fact only quasi-adiabatic. This is because they are not logically reversible, which means that they have some non-adiabatic losses. However, using the concept of Reversible Computation, which was introduced in section 2.6, fully adiabatic, reversible processing gates could be constructed. It has been shown that complex PFAL gates can be constructed so that they are fully- reversible [Will08b]. This means that arbitrary reversible gates with up to four inputs can be constructed. Because it is also possible to drive the asynchronous control logic in the reverse direction by inverting the handshake signals, there is enormous potential for the creation of reversible Asynchrobatic logic systems.

The potential for reversibility was alluded to in the initial paper describing PFAL [Vetu96], but in various subsequent works which utilise PFAL [Amir00], [Amir04], [Blot04], [Fisc05], [Fisc06] & [Teic07], this potential does not appear to have been explored any further. The creators of EACRL also considered reversibility [Varg01a]. The experimental implementation of a Toffoli gate [Fred82] using PFAL technology [Will08b] demonstrates that structures from the Reversible Logic paradigm can be viably created in PFAL, and that for an ideal waveform, it reduced power consumption by about two- thirds. Conceptually it is only a small step to move from driving these structures with ideal waveforms, to using SWC circuits from Asynchrobatic Logic. Currently unpublished experimental results suggest that Asynchrobatic Logic with a fully-reversible PFAL data-path operates with lower power consumption than a PFAL data-path with irreversible losses.

Reversible logic design is a very different paradigm from traditional logic design, as most logic functions like AND and OR are not reversible. The simplest familiar logic function that can easily be made reversible is XOR. By

two inputs and two outputs is created, this results in a Controlled-NOT, where the one signal is inverted between input and output depending upon the value of the other signal, which passes through always passes through unmodified. Unfortunately, this gate is not universal. However, a universal gate can be obtained by extending this idea to a three-input, three-output gate where the two signals always pass through unmodified, and the other signal is inverted only if both the unmodified signals hold values representing “True”. This is called a Controlled-Controlled-NOT or a Toffoli Gate. Table 5.1 shows the truth-table for a Toffoli Gate, and a Toffoli Gate symbol (after [Feyn00]) is shown in Figure 5.11. A B C A' B' C' 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0

Table 5.1: Truth-table for a Toffoli Gate [Feyn00]

Figure 5.11: Controlled-Controlled-NOT (CCN) or Toffoli Gate Symbol [Feyn00]

A B C A' C' B'

Figure 5.12 shows a logic-level schematic of how a Toffoli Gate can be implemented in PFAL. It should be noted that because the PFAL implementation uses a dual-rail logic, a port's labels refer to a pair of wires, one asserted high, the other asserted low, for example the port labelled “A” consists of two signals, “A_H” and “A_L”.

Figure 5.12: Schematic of a PFAL Toffoli Gate [Will08b]

The Toffoli Gate, contained within the outer box, is created from six PFAL gates (one within each of the six inner boxes). Each of these PFAL gates has two separate functions with separate evaluation trees, there is a forward-path function, and a recovery-path function. Ten of these functions are just buffers, and the other two, which form the Controlled-Controlled-NOT (CCN), are implemented using an AND-XOR gate. The NMOS tree for this is shown in Figure 5.13. As is alluded to by the way the schematic is drawn in

Vpc#1

Vpc#2

A

A'

B

B'

existing over two adjacent pipeline stages, although in certain circumstances, it is possible to put a sequence of functions closer together by using the rather esoteric concept of the reversible function existing in the space between two pipeline stages.

Figure 5.13: Evaluation tree for AND-XOR function [Will08b]

It should be evident from the evaluation tree for the AND-XOR gate, that in any transistor based design, the Toffoli Gates implemented are still not entirely loss-less. This is due to small amounts of charge that will be retained on the three internal source-drain connections within the evaluation or recovery logic.

Moving to reversible logic is not without costs. It adds many extra complications. The implemented functions must be invertible, and to accommodate the recovery path, require feedback from the outputs of the subsequent stage. The Toffoli gate is only a starting point, and any invertible function of four inputs or fewer can be implemented using PFAL gates. This may have applications to cryptographic algorithms that use four-bit substitution boxes, as these could be implemented in fully reversible logic, possibly improving resistance to Differential Power Analysis (DPA).

Vpc Z_H Z_L A_H C_L A_L B_L B_H C_H C_L

Figure 5.14 shows how the performance of PFAL gates varies depending upon whether they include a recovery path, which makes them reversible, or whether they are non-reversible, quasi-adiabatic gates with only the forward evaluation path.

The upper graph shows the currents flowing into and out of two adjacent stages. There are a pair of signals labelled “I(VPC5)” and another pair labelled “I(VPC6)”. The red and green signals chart the performance of the reversible circuit, whilst the magenta and blue signals chart the performance of the non-reversible circuit. The current supplied to the reversible circuit can be seen to be greater, which is to be expected because it includes more devices and has has a higher capacitive load, but the current recovered from the reversible circuit is also greater.

The lower graph shows the output voltage on the asserted high “C” output of a Toffoli gate. It can be seen that the output voltages of the non- reversible versions do not track the power-clock voltage all the way to ground, but switch later as the inputs to the evaluation stage change.

5.9 Summary

In this chapter Asynchrobatic Logic has been introduced. It has been shown that once the extra cost, in terms of power, has been amortised by the increased power efficiency of the data-path, that it is capable of lower power operation than asynchronous systems. The amortisation of the extra power is performed by having a wide data-path. In the example given, it was shown that a 16-bit ECRL data-path would never make sufficient savings, but that with a 32-bit ECRL data-path, if more that 70% (23-bits) of the data bus changed during each transaction, then Asynchrobatic logic would be more efficient. It should be noted that ECRL is a quasi-adiabatic logic family, so by using fully adiabatic, reversible logic structures, it is likely that the data-path's power consumption can be further lowered.

The concept of fully reversible PFAL gates that can perform data processing was also presented. A reversible Toffoli gate was implemented using PFAL, and its performance, using ideal adiabatic charging, was compared against that of a non-reversible AND-XOR gate. The reversible Toffoli gate used about two-thirds less power than the non-reversible AND-XOR gate.