A review of asynchronous logic

3.1 Introduction

In this chapter, the basic concepts of asynchronous logic will be introduced. Since this work was more focused upon adding a basic asynchronous controller to an adiabatic data-path, the depth of coverage of asynchronous logic is lower.

Like “Adiabatic”, the term “Asynchronous” is also of Greek origin. It literally means “without alike time”, but in the context of microelectronic design, its meaning has evolved to mean without a global time reference (a clock). Thus asynchronous logic is a logic design style that does not use a clock to synchronise the performance of operations. This is in stark contrast to the majority of digital circuits currently in existence, which have been designed using a synchronous design methodology. Unlike them, asynchronous logic does not use a ticking clock, but instead it uses a handshaking protocol to facilitate inter-stage communication.

This can have several benefits when compared against traditional synchronous designs. For Asynchrobatic Logic, the most important of these documented benefits are lower power and potential for design reuse. However, in some of the proposed applications, other benefits like lower electro-magnetic noise would also be of benefit [VBer94].

When compared to a synchronous system both asynchronous and Asynchrobatic systems will have the benefits of power-supply voltage tolerance, allowing lower voltage operation than would normally be possible for synchronous systems. This is because the synchronous design methodology requires its design elements, standard cells, to be characterised at fixed Process, Voltage and Temperature (PVT) conditions. The slowest of these is normally slowest process, lowest tolerable voltage and highest

temperature. Outside of the qualified range the circuits may fail due to violating setup-time requirements, with data-arriving too late to be correctly latched by a clock edge. This limits the voltage scaling that may be applied to a synchronous circuit. For both standard synchronous and standard asynchronous logic, the effect of lowering the voltage will reduce the power- consumption according to equation (3.1).

P

=

f

C

V

in which: PD is the dynamic power dissipation,

fe is the effective switching frequency,

CL is the capacitive load, and

VDD is the supply voltage.

Other low-power benefits can be illustrated by looking forward and considering a large Asynchrobatic system in comparison to an equivalently large asynchronous system and an equivalently large synchronous system. The lack of a global clock is also a major benefit. In the synchronous system, the ticking global clock would at minimum, reach a clock-gating element at the entry to each stage, and consequentially would waste energy. In the asynchronous and Asynchrobatic systems, the inactive states are just that, inactive, and as such, with no switching occurring, only leakage power will be consumed. However, in the Asynchrobatic system, there will be, on average, a quarter of the controllers in each of the charging states (“Idle”, “Charge”, “Hold”, “Recoup”). The active states (“Charge” and “Recoup”) require several operations, whilst the inactive states (“Idle”, “Hold”) require no operations. It should also be noted that for Asynchrobatic Logic, for any stage in the “Idle” state, the entire data-path has no potential difference across it from the power- supply, meaning that there is not even the possibility of having any source- drain leakage current through it! The only possible leakage current paths are gate-leakage from adjacent stages.

been published by the end of that decade [Mull59]. However, probably the most influential development was Sutherland’s invention of Micropipelines [Suth89]. These explain the control components required to implement asynchronous systems, but their hand-shaking protocol does not suit the adiabatic parts of an Asynchrobatic system. Asynchronous logic is more technologically mature than adiabatic logic, and as well as having been shown to be suitable for the implementation of complex processors [Pave94], commercial asynchronous processors are now available [Hand04].

3.2 Asynchronous signalling

There are two different types of asynchronous signalling conventions, two-phase and four-phase. Two-phase signalling simply reacts to a change of the signals, whilst four-phase signalling is dependent upon the levels of the signals. There are also two different methods for data transmission; bundled- data and dual-rail. For different reasons, the adiabatic data-path is already dual-rail, but the chosen implementation operates using principles far more akin to those of bundled-data. Whilst a brief background to both of the signalling styles and data transmission methods will be provided, this section will concentrate on, and elaborate more fully, the principles of systems based upon four-phase signalling with bundled-data. The asynchronous communication occurs between the Asynchronous Stepwise Charging controllers, and the bundled-data is held on the adiabatic data-path.

The handshaking protocols in asynchronous logic usually use two signals, a “request” from the sender to the receiver, and an “acknowledge” from the receiver to the sender.

In dual-rail asynchronous logic, a similar signalling protocol to that described for adiabatic logic is used. These states are used to perform completion detection so that for a dual-rail data-path, the next stage will be activated only when all dual-rail outputs have a valid state. Without error

detection, this requires an OR operation on each pair of bit-lines, and the AND of these results. Whereas the bundled-data method assumes that a delay in the control logic will match the worst delay in the data-path, and uses this to delay the sending or request and acknowledge signals.

Two-phase asynchronous signalling is dependent upon structures that are edge-triggered. An edge (either rising or falling) on the request signal is used to signal that data is available. The receiver responds with an edge (again either rising or falling) on its acknowledge signal. There is therefore no information about the state of the communication channel held in its signals' levels.

Figure 3.1: Four-phase handshaking protocol [Pave94]

Four-phase signalling fits much better with the adiabatic charging and discharging cycle. Whilst it could be possible to use dual-rail signalling, as this is available in the adiabatic data-path, this would introduce more complications than would appear to be necessary. Figure 3.1 shows the four-

Acknowledge