Verilog modelling

At its simplest, the Verilog model can be made using a series of standard latches with data-processing inputs. These are clocked by the outputs of modelled asynchronous components. These are used to represent the various local power-clocks. The essential part of modelling Asynchrobatic pipelines, and where it differs from the modelling of static CMOS, is to return the output or outputs of the data-path to an invalid state on the falling edge of the simulated power-clock. For the single rail version, the invalid state can be an output of either undefined (1'bx) or high-impedance (1'bz), or the output could just return to logic zero. The third option is probably the least preferable since it would make it difficult to disambiguate between a zero and an error condition. Code Segment 1 shows a single-rail Verilog implementation of a two-input AND gate. Figure 6.1 shows, for a two-input AND gate, how the single-rail Verilog can be conceptualised as a logic function merged into a resettable D-type Flip-Flop, followed by a tristate output driver, with both controlled by the same simulated power-clock signal. This is the novel contribution because by capturing both the rising and falling edges of the power-clock, it can capture pipeline timing errors, something that would be missed if the design was simulated using standard flip-flops or latches.

// Single-rail, functional

// representation of an adiabatic // two-input AND gate

module Buffer (A,B,Z,PClk,Rst0) input A, B; // Inputs

input Pclk; // Simulated Power-Clock input Rst0; // Reset (active low) output Z; // Output

// Detect Reset, otherwise

// Simulate Charge & Hold stages

always @(posedge PClk or negedge Rst0) if (~Rst0)

#`RESET_DELAY Z <= 1'bz;

else

// Define output function #`STAGE_DELAY Z <= A & B; // Simulate Recover & Wait stages

always @(negedge PClk)

#`STAGE_DELAY Z <= 1'bz;

endmodule

Code Segment 1: Single-rail Asynchrobatic two-input AND gate in Verilog

Figure 6.1: Conceptualisation of a two-input AND gate for single-rail Asynchrobatic data-path simulation

The ideas behind the behavioural modelling of the single-rail scheme can be simply extended to dual-rail by the addition of extra wiring, and, in the majority of cases, this can be achieved by the use of regular expression substitutions.

B_H

A_H

Rst_L

PClk

Z_H

The dual-rail implementation allows state checking can also be added to detect and report invalid circuit operation. However, its effectiveness will depend upon how the complementary outputs are generated. For components like multiplexers, the state checking is more complex, because the unselected input does not require state checking. The dual-rail method can then be replaced by switch-level models. For the dual-rail version, the idle state can be modelled by the pair of complementary outputs both being driven to the same logic value (normally both at zero), although there is nothing to prevent these outputs both returning to either undefined or high- impedance. Code Segment 2 shows a dual-rail buffer, which also includes basic checking that the complementary inputs are not equal on the rising edge of the power-clock.

// Dual-rail, functional representation // of an adiabatic buffer

module Buffer (A_L, A_H, Z_L, Z_H, Pclk, Rst0) input A_L, A_H; // Inputs to be buffered input Pclk; // Simulated Power-Clock input Rst0; // Reset (active low) output Z_L, Z_H; // Outputs

// Detect Reset, otherwise

// Simulate Charge & Hold stages

always @(posedge PClk or negedge Rst0) if (~Rst0) begin #`RESET_DELAY Z_L <= 1'bx; Z_H <= 1'bx; end else begin

if (A_L == A_H) // An invalid state

$display("Input violation in %m at %t",$time); // Define both versions of output function #`STAGE_DELAY Z_L <= A_L; Z_H <= A_H;

end

// Simulate Recover & Wait stages

always @(negedge PClk) begin

#`STAGE_DELAY Z_L <= 1'b0; Z_H <= 1'b0;

end

endmodule

Code Segment 2: Dual-rail Asynchrobatic buffer in Verilog

As previously noted, the major benefit that Verilog has over VHDL is its switch-level modelling. This would allow the data-path to be modelled using primitive devices that represent the MOS switches, but with a major increase in simulation speed. The primitive Verilog constructs that could be used are nmos, pmos, tranif0 and tranif1. Due to limitations of the Verilog simulator used (Icarus Verilog [Icar02]), these models were not fully implemented, and were not necessary, as the behavioural models were more than adequate. However, the potential applications where these switch-level models would be useful are HDL modelling of power consumption, and as a

schematic source in applications such as Layout Versus Schematic (LVS) checking.

A minor issue encountered when attempting to model such circuits using HDLs is that static CMOS circuits are required for the control structures and adiabatic circuits are required for the data-path. Since various functions, like, for example, an inverter could exist in both design styles, and are identically named, but not interchangeable, it is important to use a naming system, or programming language concepts like package scope, to ensure that the different logic types are kept separated. This may be an area where the use of VHDL would have advantages over Verilog.

For the automated implementation of more complex functions, it would be possible to use a pre-processor, to take the description of a cell's function, and pass this through a OBDD minimiser and optimiser to determine the minimum tree size required to form that function. If the technology were commercialised, then this step would need to re-order and re-label the inputs and outputs to map the required output function onto an appropriate cell in the library. For example, for a single-input gate, there is only one possible circuit design, but the inverter is a buffer with its outputs' assertion levels exchanged. For a two-input gate, the XNOR function can be obtained from the XOR function by simply exchanging its outputs' assertion levels, and the AND, OR, NAND, NOR, and versions of these with a single inverted input can all be obtained from an AND gate by exchanging the assertion levels of either the inputs, the outputs or both.