Other Regular Forms

In addition to gate matrices, there are many other ways to generate layout automatically from

higher-level specifications. Diffusion line tracing is a method that strings together the transistors of a MOS design, connecting sources to drains as far as possible, and then routing the remaining polysilicon and metal connections [Nogatch and Hodges]. The storage/logic array [Goates, Harris, Oettel, and Waldron] is an enhanced PLA that contains memory elements so that state can be captured internally rather than having to loop around the outside of the array. The Tpack system allows designers to identify areas of a small layout that will be repeated according to a personality matrix [Mayo]. This allows large but regular circuits to be easily designed. Other methods are constantly being invented for the

construction of layout. As these methods improve, they will approach the quality of hand layout and earn their place as the key component of silicon compilation.

4.2.5 Compaction

The last synthesis tool to be discussed under the category of cell contents manipulation is compaction, which removes unnecessary space from a design by moving everything to its closest permissible

distance. This step can be done on a completed chip but is usually done on a cell-by-cell basis to recover unused space as soon as possible.

The simplest compaction method, called one-dimensional compaction, works by squeezing space along the x axis and then along the y axis. This is repeated until no more space can be recovered [Williams;

Hsueh and Pederson; Weste; Entenman and Daniel]. One-dimensional compaction is simple to do, runs fairly quickly, and will recover most of the savable space. More advanced techniques attempt to save additional space by jogging wires or moving components; thus they are performing placement, routing, and compaction all at once. These methods have combinatorial work to do and produce only slightly better results than simple compaction methods.

One-dimensional compaction uses information about components and their connecting wires. The wires that run perpendicular to the direction of compaction link a set of components into a single track that will adjust together. Components and tracks are typically represented with a graph that shows the

movable objects and their movement limitations. For example, in Fig. 4.5 the track with components A, B, and C will move together when x-axis compaction is done, as will the track with components E, F, and G. Although a track may run for the entire length or width of the cell, it may also be treated as a locally connected piece of layout. This allows all unconnected parts of the design to compact properly,

independent of other layout that may originate in the same row or column.

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FIGURE 4.5 One-dimensional compaction (along x axis): (a) Layout (b) Minimum-spacing matrix (c) Minimum-spacing graph.

Compaction is done by adjusting the coordinates for each track. However, when virtual grid design styles are used, the initial spacings are all on a dimensionless grid, so the compaction process becomes one of assigning real coordinates to the tracks [Weste; Entenman and Daniel]. Regardless of the initial

coordinate system, one-dimensional compaction must determine the minimum distance between two tracks of layout. This can be done by scanning all combinations of components in both tracks and

computing the greatest design-rule spacing that is necessary. In Fig. 4.5, for example, transistors A and G must be 7 units apart from centerline to centerline, based on a 3-unit minimum diffusion spacing; 3 units between the centerline of A and its diffusion edge; and 1 unit between the centerline of G and its

diffusion edge.

Each component must remain at a particular distance from its neighboring components, and this

collection of distance constraints is found in the graph. Construction of the graph can be augmented by connectivity information so that electrically equivalent components are allowed to touch or overlap [Do and Dawson]. There can also be weighting factors in the graph to address nongeometric considerations such as the desire to keep diffusion lines short [Mosteller]. The graph, which has nodes for each

component and arcs for each spacing rule, can be used to determine quickly the allowable separation of two tracks. Transistor A does not interact with objects E and F because they are not on the same level.

Nevertheless, it is necessary to check for objects that are diagonally spaced because they may interact.

Scanning the rest of these two columns shows that the 7-unit spacing is the worst case and thus defines the limit of compaction.

The previous example can also be used to illustrate the need for repeated application of one-dimensional compaction. The first x compaction places the two columns 7 units apart which is limited by the location of transistors A and G. It is possible, however, that during y compaction transistor G will move down but transistor A will not, due to other constraints. Then, the second pass of x compaction will bring the two columns to 6 units apart, defined by the minimum distance between wire B and transistor G.

One-dimensional compaction is usually fast enough to be done continuously until there is no improvement made in either direction.

Although this method seems simple, there are pitfalls that must be observed. Weste observed that it is not sufficient to check only the next adjacent track when compacting. Pathological cases found in some environments cause layout two tracks away to present more severe constraints than does the layout in the immediately adjacent track [Weste]. Therefore the construction of the constraint graph must extend beyond the boundary formed by tracks of components, and must evaluate the worst-case spacing among all combinations of objects.

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Another problem that can arise in alternating axes during one-dimensional compaction is that motion along one axis can block more significant motion along the other. With an interactive system, this can be controlled by having the designer specify areas and directions of compaction [Williams; Scott and

Ousterhout; Mori]. Some systems allow designers to augment the spacing graph with their own constraints [Do and Dawson; Mosteller]. When these additional user constraints create an overconstrained situation, Do and Dawson leave the layout uncompacted with the hope that the orthogonal compaction phase will remove the blockage. Another feature that their interactive system provides is the notion of a fence that designers place to prevent unwanted mingling of components.

Regardless of interaction flexibility, the problem remains that one-dimensional compaction has no global information to help it achieve the best results. What is needed is a way to relate the x and y constraints so that the sequencing of the process uses all of the available information.

Both x- and y-axis constraints can be incorporated into a single network to enable more global compaction [Watanabe]. This network has arcs between all components that may interact during

compaction. These arcs are tagged to indicate whether they can act alone or can work in conjunction with a dual constraint that runs in a perpendicular direction. This notion of a dual constraint enables

diagonally spaced components to compact in either direction. For example, two contacts that must remain 3 units apart can stay 3 units away in x, or 3 units away in y, but when they are placed on a diagonal it is not necessary to enforce both constraints. This is because diagonal constraints are spaced farther apart than is actually necessary.

Optimizing a two-axis constraint network involves a branch-and-bound technique that iteratively finds the longest path in either direction and removes one-half of a dual constraint to shorten that path. This can take much time on a large network, so it is useful to reduce the initial graph size as much as possible.

Watanabe found a property of uncompacted layout that helps to reduce this network: If every component is viewed as a vertex and every wire as an edge, the initial design forms an uninterrupted area of

polygons. A constraint between two components is not necessary if those components do not border on the same polygon.

Humans often compact by jogging wires so that components can tuck into the tightest space. This can be done automatically by splitting wires at potential jog points so that the two halves can move independently. One observation is that good jog points occur where two parallel wires are connected by an orthogonal wire [Dunlop].

The orthogonal wire can be jogged to save space (see Fig.

4.6). Of course, jogs can be placed anywhere and the most general jog-insertion technique is to

remove all wires and reroute them [Maley]. Routing methods will be discussed later in this chapter.

FIGURE 4.6 Jog insertion during compaction: (a) Before (b) After.

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As a final consideration, it is possible to use simulated annealing as a model of compaction [Sechen and Sangiovanni-Vincentelli]. This technique, which is useful for many synthesis tasks, makes severe

adjustments to the layout at the beginning and subsequently damps its action to make smaller changes, thus mimicking the annealing process of cooling molecules [Metropolis et al.]. By making component placement and orientation changes between compaction passes, each change can be seen either to help or to hurt the compaction. Major changes are tried first so that the overall layout configuration can be

established. The minor changes are made last, in an attempt to save the small bits of space. This method consumes vast amounts of time but achieves very good results.

A more global issue in compaction is how to do it in a hierarchical environment. Typically, leaf cells are compacted first and then composition cells are adjusted to squeeze space around the leaf instances

[Ackland and Weste]. This can cause problems when leaf-cell compaction realigns connection points, causing intercell connections to be broken. Although a hierarchical-layout constraint system, such as that in Electric (see Chapter 11), will keep these connections safe, most systems must do pitch matching (discussed later in the chapter) to ensure that hierarchical compaction will produce valid results [Weste;

Entenman and Daniel].

Compaction is useful in improving productivity because it frees the designer from worries about proper spacing. With any compacter--even a simple one-dimensional compacter--layout can initially be done with coarse spacing so that the circuit can be better visualized. The designer is free to concentrate on the circuit and need not waste time scrutinizing the layout for unused space. Also, the existence of a

compacter makes it easier to produce cell-contents generators because precise layout issues can be deferred. Finally, a compacter can be used to convert layout from one set of geometric design rules to another [Schiele].

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Computer Aids for VLSI Design

Steven M. Rubin

Copyright © 1994

Chapter 4: Synthesis Tools

Section 3 of 7