A Low-Power Interface Design for Intelligent Sensor Nodes Utilized in Wireless Sensor Networks

Rochester Institute of Technology

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2006

A Low-Power Interface Design for Intelligent

Sensor Nodes Utilized in Wireless Sensor

Networks

Shruti Lakdawala

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Recommended Citation

A Low-Power Interface Design for Intelligent Sensor Nodes

Utilized in Wireless Sensor Networks

By

Shruti Lakdawala

A Thesis Submitted in Partial Fulfillment of the Requirements for the Degree of

Master of Science in Computer Engineering

Approved By:

Fei

Hu

Supervised by

Dr. Fei Hu

Department of Computer Engineering

Kate Gleason College of Engineering

Rochester Institute of Technology

Rochester, New York

February 2006

Dr. Fei Hu, Assistant Professor

Department of Computer Engineering, RIT

Daniel Phillips

Dr. Daniel Phillips, Assistant Professor

Department of Electrical Engineering, RIT

Pratapa Reddy

Dr. Pratapa Reddy, Professor

Thesis Release

Permission

Form

Rochester

Institute

of

Technology

Kate

Gleason

College

of

Engineering

A Low-Power Interface Design for Intelligent Sensor Nodes Utilized in

Wireless Sensor Networks

I,

Shruti

Lakdawala, hereby

grantpermissionto theWallace Memorial

Library

to

reproduce _mythesisinwholeor part.

S.L

Shruti Lakdawala

03/02/2006

Acknowledgements

My

sincere gratitude to Dr. Hu andDr.

Phillips,

who made itpossible for meto do this

research

by

_providing mewith the_necessary resources andtheirvaluable guidance from

time totime.

Also,

Dr.

Reddy

for hisvaluable commentstowards

improving

_myresearch.

I am _extremely grateful to all of them for

being

_{understanding} and _encouraging

throughoutthe courseof_mythesis.

Iwish to thank themembers of

Tinyos-Help

forum thathelped me resolve_myqueriesin

TinyOS as well as NesC.

Also,

Cypress Technical Support as well as the PSoC

Developers

forum,

_{for making} all the PSoC technical resource available and for their

quickresponseto_{my PSoC}queries.

I am _very grateful to _my

family

for

being

patient, understanding and supportive

throughout the course of _{my Masters} curriculum. I would also like to _specially thank

Jyoti and Kush Lakdawala for their generosity and hospitality.

Finally,

_{my friends for}

Abstract

A Low-Power Interface Design for Intelligent SensorNodesutilizedin Wireless

Sensor Networks

Thisthesis describes a means _{for performing} complex event detection at a single sensor

node of a wireless sensor network

(WSN) by

interfacing

a low-power mixed signal

Programmable System on

Chip (PSoC)

to aMICA2 wireless sensornode. The proposed

system helps to reduce the overall power consumption of_{the node,}

by lending

it the

advance computational _capability to process a significant amount ofdata at the node

rather than

transmitting

it. This allows the node to "intelligently" monitor a signal for

impending

events insteadof

transmitting

the"raw"signal to thebaseconstantly.Previous

work

by

others has indicatedthat

lowering

the transmissiondatarate lowersthehighcost

of transmission power

[41],

[42]

in a node

thereby

lengthening

the node life and,

ultimately,

increasing

thereliabilityofthenetwork [43].

This work implements a threshold technique which controls the data transmission rate

depending

on the value ofthe monitored signal and a cardiac _monitoring system that

performs complex computations at the node for the detection ofeither a skipped heart

beat or a reduced Heart Rate

Variability (HRV)

whereupon the relevant unprocessed

signalis transmitted to the base station for directobservation. Aperformance analysis of

the systemdemonstrates thatthereis a reductioninthepowerconsumption oftheoverall

sensor node and a significant reduction in data transmission rate which also results in a

Table

of

Contents

Thesis ReleasePermission Form i

Acknowledgements ii

Abstract iii

TableofContents iv

ListofFigures vi

ListofTables vii

1. Introduction 1

1.1 Introduction: 1

1.2 ProblemandMotivation: 2

1.3Proposed Design: 4

2. Background 8

2.1 Power-efficient Sensor Networks: 8

2.2 PSoC Mixed Signal Array: 10

2.3 Related Research inPhysiologicalApplications: 1 1

2.4Cardiac

Monitoring

Systems: 14

2.4.1 Heart Rate

Variability

14

2.5.2

Measuring

HRV 15

3. MICA2Hardware/Software 17

3.1 Hardware Platform IV

3.2 Mica2 Software Platform: 20

3.2.1 TinyOS: 20

3.2.2 NesC: 22

4. Programmable

System-on-Chip (PSoC)

23

4.1 PSoc HardwareFramework: 23

4.1.1 Digital Blocks: 25

4.1.2

Analog

Blocks: 26

4.2

Programming

Environment: 28

5. Interface Design 31

5.1

Programming

PSoC to supportUART serialcommunication 32

5.1. 1: Amplifier 33

5.1.2:

Analog

to DigitalConverter

(ADC)

33

5.1.3: UART Receive/Transmit Blocks: 35

5.1.4: The Device Editor

Placing

andRouting: 36

5.2. UARTtoRS232 ConversionatPSoCend 37

5.3 TOS Message Structure: 39

5.3.1 Packets: 39

5.3.2 TOS Message Structure: 40

5.3.3 PSoC andTinyOS Message Structure: 43

5.4 MICA2programming: ₄₇

5.5

Setting

_up theBase Station: 48

6.

Thresholding

andPhysiological Application 50

6.1 Thresholding: ₅₀

6.2Cardiac

Monitoring

System: 52

6.2.1 Concept of_monitoringthecardiac signal withinthePSoC: 52

6.2.2

Measuring

theRR-Interval: 53

6.2.3

Measuring

aSkipped beat: 54

6.2.4

Placing

and

Routing

intheDevice Editor: 55

6.2.5 Application Editor: 57

6.2.6 For

Measuring

Standard Deviationover a period of5 Minutes: 58

7. Results andPerformance Analysis 60

7.1

Thresholding

Application: 60

7.2 Cardiac

Monitoring

System: 64

8.

Energy

Modelfor

Single-Hop,

Single-Sender Network 68

8.1

Energy

ModelofIndividualComponents: 68

8.1.1 Sensor

Energy Consumption;

E(S)

68

8.1.2 Microcontroller

Energy

Consumption;

E(MCU)

68

8.1.3 Transceiver

Energy

Consumption: 69

8.2 Model 1: Without

interfacing

PSoC 70

8.3 Model 2: With interfaced PSoC 71

8.3.1 PSoC

Energy

Consumption; E(PSOC)

72

9. Future Enhancement 76

9.1 Power ReductionwithintheInterface 76

9.2

Wakeup/Sleep

Protocol 78

9.3 Wireless Vital Signs

Monitoring

Device 78

9.4

Integrating

intoaSystemon

Chip

79

10. Conclusion 80

Bibliography

81

List

of

Figures

Figure 1.1: General Block DiagramofaSensor Node 3

Figure 1.2: Block DiagramoftheProposed System 6

Figure 2.1: The effect of

increasing

datarate and

hop

count on reception ratio 12

Figure 2.2: Effectof

increasing

datarate and numberofsenderswith 1 receiver[18] 13

Figure 2.3: Wireless EKG developed

by

Codeblue

[18]

13 Figure 2.4: Cardiac

Signal,

Illustrating

theRR Interval 14

Figure 2.5: Tachogramof normal/

healthy

subject ₁₅

Figure 3.1: MICA2 Platform

[40]

withinterfacesto thesensorboardandthebatteries.. 17

Figure 3.2: SnapshotofMICA2mote supplied

by

Crossbow Incorporated.

[40]

18

Figure3.3: Componentswiredtogether tobuildtheBlinkapplication

[25]

21

Figure 4.1: PSoC Block DiagramofCY8C274x3

[27]

₂₃

Figure 4.2: Blockdiagramoftheconfigurabledigital block

[27]

26

Figure 4.3: Block diagramoftheconfigurable_analogsystem

[27]

27

Figure 5.1:

(a)

MIB510CAserial _gateway

(b)

withattachedMICA2 mote.[29] 31

Figure 5.2: Block diagram showingthedigitaland_analogperipheral blocks 32

Figure 5.3: PGA Block diagram in PSoC

[30]

33

Figure 5.4: Simplified Block diagram oftheIncremental ADCin PSoC

[31]

34

Figure 5.5: Internal Block DiagramoftheUART ReceiveandTransmit blocks.

[32]

35 Figure 5.6: Peripheralcomponentsandthe_{internal routing}ofthe signals 36

Figure 5.7: Pin DiagramofPSoC after_programmingtheperipheralblocks 37 Figure 5.8: Schematic diagram for converting UARTsignaltoRS232 signals 38

Figure 5.9: SnapshotofMICA2 interfacedwithPSoC 39

Figure 5.10: Example Raw Data Packetstobe senttoMICA2 43

Figure 5.11: Flowchart for PSoC sendingsampleddata using TOS Message 46 Figure 5.12: Block Diagramofthe implementedsystem 47

Figure 5.13: showsthe_{wiring diagram}ofcomponentTOSBase.

[25]

48

Figure 5.14: Base Station set-up 49

Figure 6.1: Receivedwaveform displayedatbasestation 51

Figure 6.2: Sampled cardiac signal

being

displayedatthebase station 52

Figure 6.3:

Measuring

the_{RR-Interval using PSoC} 53

Figure 6.4: Device Editor Viewfora cardiac_monitoringsystem 56

Figure 7.1: Waveformatbasestation aftertheimplementationof

thresholding

64

Figure 7.3: Distortedwaveform received atthebasestationdueto droppedpacket 66

Figure 8.1: First Order Radio Model. Source

[47]

69

Figure 8.2: Block DiagramofRemote NodeandBase Node ina_single-hop, single node

n/w 70

Figure 8.3: Blockdiagram oftheRemote Nodewith_{PSoC along}withtheBase Node. . 71

Figure 9.1:

(a)

Flip-flop

without gated_clock; (b):

Flip-flop

with gated clock 77

List

of

Tables

Table 1.1: Approximate Power ConsumptionofMOCA2

[47]

4

Table 2.1: Hardwareplatforms

("Motes")

fromCrossbow

Technology

Inc.

[40]

9 Table 3.1: Powerconsumptiontablefor MICA2.

[44],

IllustratedwithChart 20

Table 4.1: Available PSoC Devicegroups.

[27]

25

Table 5.1: Packet StructureinTOS Message Structure

[34]

40

Table 5.2: Field descriptioninpacketsofTOS Message Structure. Source:

[34]

42

Table 7.1: Powerconsumptionin PSoC for implementationofthe

thresholding

algorithm

60

Table 7.2: Evaluationof powerconsumptionwithandwithoutPSoC interface. Model 1:

withoutPSoC andModel2: withPSoC 63

1. Introduction

1.1 Introduction:

Wireless Sensor Networks

(WSN)

are formed

by

a number of sensor nodes that are

deployed overa region for monitoring datawirelessly. Eachnode _{is normally}comprised

of a microprocessor, transceiver and a sensor.

Ongoing

developments in wireless

communication,integratedcircuitdesignandMicro-electro-mechanicalsystems

(MEMS)

have resultedin _small,

low-power,

low-cost sensorsand electronic

devices,

which makes

establishment of a WSN a reality. A single wireless node relies on its limited local

resources and has minimal _{capabilities,} however when a number ofthis type of sensor

nodeare distributedoveraregion

they

areable to extendtheoverall capabilities

by

_using

advanced _networkingprotocols to transfer_{data autonomously from} one node to another

and _arbitrary remote destinations. As a _{result, the} wireless network comprised ofthese

nodescan possess substantial_{processingcapability [49].}

WSNs are

becoming increasingly

versatile with the miniaturization ofthenodes and can

be used for a wide range of applications [1].

They

can be used for environmental

applications: the air, water, soilconditions which affectthe crops and livestockcouldbe

monitored continuously; habitat monitoring: the seasonal migrationofanimals and birds

couldbe tracked

by

tagging

them with a sensor node; disastermanagement: forest fires

canbe

detected,

alertingtheauthoritiesbefore

they

spread_{uncontrollably;} indoor_security

andmaintenance: In

homes,

offices andhospitals

they

couldbeused to monitor and

help

military applications: _{surveillance,}

tracking

_{soldiers, damage assessment;} structural

monitoring;physiological monitoring: _wherebythepatients couldbetaggedwithwireless

sensor node that would makes patient _mobility possible for patients that need to be

monitored over anextendedperiodoftime.

In particular, WSNs have enormous potential benefits in the area of physiological

monitoring orbiomedical applications [38]. It affords patient _mobilitythat can facilitate

physiological _study ofthepatients or subjects

during

theirnormal

day

to

day

activities.

Remote physiological _monitoring for vital signs such as blood _pressure,

electrocardiogram,pulseand

body

temperature enables patientstohave a_{better quality}of

provided care and

help

maintain their health. It is useful for diagnostic and research

purposes _whereby, a collection ofdata from subjects is required over a

long

period of

time. A good example is the _study ofHeart Rate

Variability

(HRV)

[3] [20]

ofsubjects

overa periodof24hours forthe_studyoftheriskofheartattacks.

1.2 Problem

and

Motivation:

The generalarchitecture of awireless sensor node _generallyincludes _sensor, control and

communication modules _along with a power subsystem. The sensor module is

responsible for data acquisition and _{any necessary} signal conditioning. The control

module provides the network protocols and controls the sensor and communication

modules. The communicationmodule handlesthe wireless transmissionand receptionof

data/sensor readings. The powersubsystem is responsible for providing powerto all the

Antenna

M

'/;...'.

_&__.

.. X ;-_ ::?-;1

Limited Power Source

Figure 1.1:General Block Diagramof aSensor Node

The finite power budget of an individual node is a _{primary design} constraint for

applications _{requiring detailed monitoring} over a

long

period of time _using wireless

sensor nodes [36]. A single node depends on a _{relatively limited} power source, which

may be

inconvenient,

expensive orimpractical to replenish.

Hence,

increasing

thepower

efficiencyofindividual sensor nodeis importantforaWSNnodedesign.

The

key

to _reducing power consumption in individual nodes is to reduce the amount of

data transmitted _{wirelessly because} radio transmission

typically

consumes a major

percentage of total power consumption. Based on _{this premise,} Table 1.1 shows the

power consumptioninaMICA2 sensornode utilizedinthis work.It canbeobservedthat

POWER SPECIFICATION

Processor Power

FullOperation

SleepMode

Radio

28.8mW

28.8 MvV

ReceiveMode

Transmit Mode

SleepMode

SensorBoard

28.8mvV

43.2mvV

7.2 it-:1

Full Operation

SleepMode

18.0mvV

[image:13.517.172.347.42.239.2]

18.0 m'-v

Table 1.1: Approximate Power ConsumptionofMOCA2 [47].

It is well known that extensive research is

being

carried out in the reduction of

transmissionoverhead

including

power associatedwithdatacommunication[1 1][13]. As

mentioned

by

Pottie and Kaiser in their discussion of wireless networks

[2],

the

computation cost can be several orders lower than the communication cost at an

individualnode; therefore local processingofthe datapoints and

transmitting

fewer data

bitsover_{the network, especially}overa

long

distance,

would save asubstantial amount of

power. Constraintsonthis line ofthoughtconsist ofthe computationalcapabilities within

an individual _node, limited memoryresources and _any external custom amplification or

filtering

circuitry necessary foraparticular_sensingmethod ortechnology.

1.3 Proposed Design:

This thesis proposes

interfacing

a

highly

versatile _{PSoC Mixed-Signal array} with a

wireless sensor node

MICA2,

to extendthecomputational capabilities of_{the node,}while

signal) components that are

typically

used in embedded systems. It also has a built in

microcontrollerwhichintegratesand controls alloftheprogrammedcomponents. Ithas a

unique _capability of_{routing analog} as well as digital signals in amanner such that

they

can be used as trigger to different analog/digital blocks as per the designer's

requirements. This flexible feature of

having

configurable mixed-signal

blocks,

whose

signals can be routed as

desired,

makes the PSoC an _extremely versatile device to

incorporate in the design of a system for the detection of complex events.

Efficiencies,

compared to the design of a similar circuit _using separate _analog and/or digital

components, are _potentially realizable in terms of_{simplicity, energy} and overall circuit

real-estate. Because of extended _{capabilities, that} can be achieved

by

the

interfacing

of

this mixed signal _array with _programming

functionality,

complex

filtering

or

triggering

functions as well as applicationspecific data compression or suppression algorithms can

be implemented at an individual node. This can facilitate increased reduction of the

volume ofdatato be transmitted overthe network_{resulting in}reducedtransmission time

and significant reductioninnetworktraffic.

Theoveralldesignofthewireless sensornode utilizedinthisworkisshownin Figure 1.2

and consists of a standard MICA2 Wireless node (Crossbow

Technology

Ine,

San

Jose,

CA)

that communicates with a PSoC (Part number:

CY8C27743)

(Cypress

Semiconductors,

San

Jose,

CA)

based sensornode over a _standard, UART-based RS-232

MICA2

Figure 1.2: Block DiagramoftheProposed_System,PSoc Mixed Signal_ArrayinterfacedtoMICA2

platform

In this _thesis, the aforementioned concept of reduction of transmission data due to

extended computation capabilitiesofthe _{PSoC is demonstrated using} atechnique where

the raw sensor readings are compared to a threshold value. If the signal _property of

interest is above a specified _threshold, it is transmitted to the base station

immediately;

however ifthecomputed signal _{property is below}the_threshold, it istransmitted afterten

counts,

during

which, the average of ten consecutive sensor _readings,

lying

below the

threshold, is computed. Thetransmissionofthecomputedvalues ofthesensordatawhich

are below the specified threshold are

thereby

suppressed, reducing transmission

data,

whichthussaves power consumptionincommunications.

In addition, the application of this PSoC enhanced sensor node in physiological

monitoring is developed and analyzed, which further demonstrates that the low-power

PSoC'scomputational capabilitiesis capable of

facilitating

reducedtransmissiondataand

networktrafficsubstantially. The Heart Rate

Variability

(HRV)

derived froma simulated

electrocardiogram

(ECG)

signalis calculated_using statistical methods. HRVrefers to the

alterations in the beat-to-beat heart rate [3]. Reduced HRV is used as a marker of

unhealthy cardiac function. The PSoC continuously processes the cardiac signal and

sampled cardiac signaltransmittedto thebasestation_onlyontheoccurrence ofaskipped

heart beat or reduced HRV. This could also be altered to send the calculated HRV or

skipped heart beat notification. This reduces continuous transmission ofthe sampled

2.

Background

2.1 Power-efficient

Sensor

Networks:

In

WSN,

the lifetime of individual sensor nodes is _{strongly dependent} on its

battery

lifetime. It is difficult to replenish the batteries of individual nodes in most of the

applications. The available _energy resource of the nodes therefore limits the overall

operation ofthe entire_network, because failure ofindividualnodes can cause substantial

topological changes to the network.

Hence,

powermanagement and powerconservation

is of utmostimportancewithinthenetwork as well asinindividualnodes.

To design a power-aware _system, the _energy consumption at all levels of system

hierarchy

must be kept at a minimum. The integrated circuit design of the node

components, the data acquisition _{system, operating} system ofthe node _processor, data

processing algorithm at application

level,

the network protocol as well as the

communication medium all must strive for overall minimal powerconsumption. Active

research is

being

conductedin all these areas forreduction in energyconsumption so as

to increasethenodelifetime and

thereby

the_qualityand_reliabilityofWSN.

A low-powermicroprocessor, transceiver, data acquisition system and external _memory

are thebasic

building

blocks ofthenode architecture. Innovative transistor technologies

and special-purpose microprocessor architectures are

being

researched and designed for

small _size,

low-voltage,

low-power and better computational performance. Similar

with main focus in low powerRFintegrated circuits _{resulting in}

improved,

low-cost RF

transceiverICs.

Different hardware _{platforms, using} alternative components for the basic blocks have

been developed and analyzed for power consumption,

flexibility,

robustness as well as

communication and computational capabilities.

[4] [5] [6] [7]

Table 2.1 showsfew wireless

nodes called

"Motes"

thatare madeavailable

by

Crossbow

Technology

Inc.

Photo Crossbow _CommonlyUsed _FrequencyRang* Processor Radio Nonvolatile

Part ID Wame TranscelwBf _Memory

MM3O0

dtscenjfiued) MIC. A:';<>nei.m 902.o9?SMHJ

Atmff C-MT(<1 CCO Atmd

(*id10 ^./<_}_'231 AT45O9041S

MPR310 8<.vflfAl)

J.1 t434,8MHj (512kB)

tlutw rued)

sssioira,*a MPfctQO

828MH2

Atfflf'l CWpcon Atr ypMio MICA2 (S33 i o'.J'IBM-: ATM9ftl28t cciooo amscmmib

StJIB:

MP8420 31} 9.031C1MMj

MPRSOQ 83te8?.;90__

Atmei O.S.COi'. Uur*

MP8SU) MCA2B0I

(S33I <S34,8MH| tf\\f.j>y m CCIOOO A145DB041B

St2kB

MPftSSC 3!593I61MHjr

Cftipcon

Atmel CC2420 Alr^l

M-*2400 _WCA/ 24W3to2483,5f/ii_*

ATM9*!28t {802.1S *3 at4s;b<m-b ($12kl

Table2.1: Hardwareplatforms_("Motes")from Crossbow_TechnologyInc._[40]

The operating system is asoftware framework forthe hardware and the network. Dueto

the _memory constraint on individual nodes, operating systems designed _explicitly for

wireless sensor network application is needed. Performanceof_{the operating} system is a

key

to further reduction in power consumption. Different _operating systems such as

Design for energyefficient network protocols are also

being

researched: MACprotocols

[11]

[12],

investigate _{reducing energy} consumption _{in periodically putting} the nodes in

sleep state instead ofthe node

being

idle;

Ad-hoc

Routing

protocols

[13],

investigate

methods for the transmitted data to take the shortest possible path to travel from the

source node to its

destination;

Clustering

Algorithm

[14],

analyze and propose _energy

efficient algorithms _{for clustering} ofnodes in _groups; Data Aggregation

Methods[15],

thatanalyze andinvestigatenovel approach forpath _sharingto save_{energyconsumption;}

Data processingalgorithms similarto those in [37].

New protocols for RF communication are

being

researched. Wireless protocols such as

Zigbee,

Bluetooth andWiFi are

being

analyzed for optimum data_{rate, range, reliability,}

cost effectiveness and low-power. Improvements in

battery

technology

are also

being

researchedto lengthenthe

battery

life.

2.2 PSoC Mixed Signal Array:

The PSoC

(programmable-system-on-chip)

Mixed Signal

Array

has been developed

by

Cypress. It is an effort towards

integrating

the _commonly used embedded system

components in one_{chip replacing} the need to have separate ICs consequently reducing

board space,power consumption and cost [17]. Itis extremelyversatile and Cypresswas

even awarded the "EDN Innovation Award" in 2001 for the 8/16 bit microprocessors

category

[16]

forthe

PSoC(TM)

product. EDNmagazine is a

leading

electronics andthe

Duetoits

flexibility

toprogram different_analoganddigitalcomponents, it has beenused

in various applications

including

physiological _{monitoring because} of its _capability to

perform complex _analogas well as digital functions. The PSoC has beenused in

building

an ECG monitoring. One such project has been described in "ECG Meter _usingPSoC"

by

Dr. Altenburg. It is designed

by

_{programming Delta} Sigma

ADC,

Low pass

filter,

counters as wellas a serial communication module onthechip.Ittransmits thedatato the

PC wherethecardiac signal isdisplayed.

2.3

Related Research in Physiological Applications:

Wearable,

unobtrusive devices thatmonitorthepatientsforvital signs are_currently

being

researched extensively. Wireless sensor network has an enormous potential in this area.

Harvard

University

is _{currently working}onproject

"Codeblue"

[18],

whichis

developing

hardware as well as software platforms _{using for} medical sensor networks _using motes

supplied

by

Crossbow Inc.

They

have also developed medical sensors such as

EKG[19],

pulse-oximeter and _{motion-activity} sensor based on the popular MicaZ and Telos mote

designs. It performs real time datacollection on thepatients'

physiological _status,which

is monitored and/or stored atthebase station.

They

are also _studying the issuesrelatedto

wireless medical-sensor networking, such as node mobility, patterns of packet

loss,

1.2

1 -.

cr _0.8 c o

Q. Q O

<D 0.6

CC <1> o> crt w

> 0.4

0.2

1 1 1 1 ' ' '

,'l

_ _._. ] pop

1

1 ._ 2-4 hops

5-6 hops *

*<

X-^_ _J _ -_+. _________.-f. ...J.

x "^-x--'

* ><

* *

* *

-->

_ __^,

# *<

i i i i i i i i i

0 5 10 15 20 25 30 35 40 45 50

Data Rate (packetsper_second)

Figure2.1: Theeffect of_increasingdatarate and_hopcounton reception ratio:_Increasingthe transmission rateleadstodegradation inreception rateduetodroppedpackets._[18]

During

their study, it was observed that the packet reception ratio i.e. the number of

received packets divided

by

the number oftransmitted packets

[18]

decreased with the

increase in the data rate, with an exception ofa single

hop

where the reception ratio

remains _pretty good _up to a data rate of 50 packets per second. A Similar trend is

observed with multiple senders with a single receiver (figure 2.2). This is because of

limitation ofthe available bandwidth for each node.

Also,

increased data rate result in [image:21.517.78.464.55.352.2]

1.2 CO CC c o Q. <D O a> cr <i> ra 2 a> > < 0.8 0.6 0.4 0.2

1 sender J-3senders -x~ 5senders -* 10senders 0

^*^>^

% i_as*...

* X

7

_x.

**fc %-yt***

EJ ^S *'"'.y

*... 'O Eh TF e _i i M

0 5 10 15 20 25 30 35 40 45 50

Data Rate (packetspersecond)

Figure2.2: Effectof_increasingdatarate and number of senders with_{1 receiver[18]}

From figure 2. land 2.2 it is observed that for a high reception _ratio, a low data rate is

encouraged, of about 5 packets per second or less for 10 senders. This could be

acceptable incase of blood pressure or pulse _oximetry sensors, but not for an ECG

monitoring system, which requires _sending constant packets of the sampled cardiac

signal.

EKG leads

EKGsensorboardk

Telosmote

[image:22.517.101.425.51.285.2]

In this thesis we demonstrate that

by

interfacing

a PSoC to

MICA2,

we are able to

develop

a wireless ECG monitoring system that sends out _{data only} when the cardiac

signal mightseem abnormal or sendcomputations ofHeart Rate

Variability,

which is an

important marker of unusual _activity of the cardiac signal. This reduces the network

traffic

by

_reducingthedatarateofan_{ECG monitoring device.}

2.4

Cardiac

Monitoring

Systems:

2.4.1 Heart Rate

Variability

Heart Rate

Variability

(HRV)

defined

by [3]

is "the beat-to-beat alterations in the heart

rate"

orRR-Interval (figure

2.4)

fluctuations. Incaseof a

healthy

_{person, the}beat tobeat

interval varies _slightly as a person inhales and exhales. Inhalation causes cardio

acceleration and exhalation causes cardio deceleration.

Hence,

there shouldbeaperiodic

variationintheintervals (figure 2.5).

-I

-T

" "

T

" ~

R< ' _RR-Interval

|>"R

|

1

!

P T P T

/ \ r\ ,,J

A

L. ....,.,

/ \

\ \ A _

i

1

____

It

Q

!s

'

Q ' S

[image:23.517.65.458.407.628.2]

REST

TACHOGRAM

1.0

0.9

0.8r

I

0.7 tr

a: 0.6

-05

0.4

N 256

mean=_{842.5 msec}

a2

= 1784msec2

100 200

[image:24.517.121.402.48.284.2]

Beat#

Figure 2.5: Tachogramof256consecutiveRRvaluesina normal/_healthysubject at supine rest[20].

Noticetheperiodicincreaseanddecrease intheRR-Interval. Thecalculated standard

deviation (in msec2) is 1784

HRV analysis is

being

_activelyresearched for riskassessment. Studies have linked HRV

to stress, inneremotional_states, suchas_anxiety, angeretc. as well asthe_abilitytopredict

survival after heart attack. Reduced HRV has been linked to the prediction of an

impending

heart attack forpatients withMI. (MI: abbreviation formyocardial infraction

inother words aheart attack)

2.5.2

Measuring

HRV

HRV is assessed _{using different} techniques. One common statistical technique is

by

measuringthe RR-Intervalofthecardiac signal and _computing thestandard deviationof

the RR-intervalsover ashort term period of5 minutes or over 24 hours. A low standard

Among

some oftheother methods ofanalyzingtheHRV

[3]

are:

pNN50 index: The number oftimes in a period ofabout 60 minutes two

consecutiveRR-Intervals varyover 50msec.

rMSSD index:

Computing

theroot-mean-squareofthedifference between

theconsecutiveRR-intervals.

MAX-MIN or _peak-valley quatification : The diffence between the

shortest and longest RR-intervals

during

inspiration and expiration

3.

MICA2

Hardware/Software

3.1 Hardware

Platform

As mentionedin chapter

2,

severaldifferent hardwareplatformshave been developed for

power consumption,

flexibility,

robustness aswell as communication and computational

capabilities.

[4]

The general architecture ofthe MICA2 _platform, supplied

by

Crossbow

Inc. is shown in figure 3.1 and the snapshot of the mote without the sensor board is

shownin figure 3.2. It uses anAtmelmega 128Lmicroprocessorasits central_processor,

a Chipcon CCI 000 _tranceiver, an external flash memory of 512KB. The pins of the

microcontrollerare brought out to a5 1 pin expansion _connector, of which some ofthem

are _{analog I/O's} that are inputsto an A/D converter (oneofthe peripheral feature ofthe

microcontroller). The sensor board can hence

directly

connect the _analog equivalent of

the sensed element to the A/D converter (ofthe _{microcontroller) for it} to be sampled. It

workson2AAbatteries.

IcyA

MMCXconnector

Logger Flash

ATMega128L

^controller AnalogI/O Otgitatt/O

1

Freq. Tunable Radio

?

Sensor Board

ZE

Batteries [image:26.517.130.411.428.634.2]

Microprocessor

Antenna

Connector

Expansion

Connector

[image:27.517.78.436.49.258.2]

Battery

Pack

Figure 3.2: SnapshotofMICA2mote supplied _byCrossbow Incorporated._[40)

Microcontroller:

The ATmegal28L

[21]

is a low _power, 8-bit microcontroller that uses CMOS

technology. It is based on AVR enhanced RISC _{architecture,} that achieves high

computational _performance,

by

_executing powerful instructions in a single clock cycle.

The architectural designachieves optimum power consumptionversus processorspeed. It

has useful peripheralfeatures

It has Harvard architecture -separate _{memory for data} as well as program code. It has

128KB of reprogrammable flash memory forprogrammemory, 4KB

EEPROM,

4KB (of

SRAM)

data memory which can be extended _up to _{64KB using} an external memory. It

operatesatspeeds of0-8MHzand voltagebetween2.7to 5.5V.

It has peripheral features such as _{timer/counters,}

ADC's,

serial communication blocks

that support

USART,

I2C protocols and master/ slave serial interface. It has different

extended standby. These features makethe _{AT128L very} useful as a central processorin

a wireless sensornode.

Transceiver:

CCI 000

[22]

is a _single-chip, RF transceiver that is designed for low current

consumption, specifically for low power, low-voltage wireless applications in mind. It

has programmable

frequency

range from

300-1000MHz,

programmable in steps of

250Hz. It has a range of about 300 feet to 500 feet

depending

on the radio band. The

CCI 000 can be programmed serially, which makes it easy to be programmed via the

microcontroller. It has a small size, low operating voltage of about 2.1 to 3.6V and

requires_{very few} external components.

Flash Memory:

MICA2uses AT45DB041

[23],

which is a512

KB,

2.5-volt serial flash memory. Dueto

the simple serial interface

design,

the reliability

increases,

the switching noise decreases

and the package size as well as the pin count decreases. It is designed for low power

dissipation,

withacurrent requirement of_{only 4mA}

during

readand2uA CMOS standby

current

Poweranalysis:

Thepower consumptionofthe MICA2'smicrocontroller andthe_{RF chip has been listed}

MoteType \/tca

-Microcontroller

T\pe

Program memory(KB)

ATmegal28

128

RAM(KB) 4

Acme Powei_(mW) 33

SleepPower (ji\V) 7$ WakenpTime Ojs) 180

Communication

Radio

Datarate_(kbpv) Modulationtype

Receive PowerSmW)

Transmit PoweratOdBtn (niWi

CClOOO 3$,4 FSK 29 42 Powei Consumption

MinimumOperation(V)

Total Active Power('aWj 89

Pw*fcon*umption mM1CA2

!*:.-.*5..t

_J

JO _r

1S

f-

::U-Table 3.1: Powerconsumptiontablefor MICA2._[44], IllustratedwithChart.

As shown in Table

1,

the transmission power ofthe radio is 42m

W,

which is a major

percentage ofthe total power consumption

(89mW)

ofthe node.

Hence,

_reducing the

wireless transmission time would result in a considerable amount of reduced power

consumption.

3.2 Mica2

Software

Platform:

3.2.1 TinyOS:

TinyOS

[8]

is an

Operating

System designed _specifically for WSN. The 4 KB ofRAM

space, whichis shared _amongthe stack, global variables and all thestatic _variables,used

intheTinyOS componentsputs a_{verytight memory}constraintonthesystem.

Therefore,

it is designed such that it minimizes the code size and facilitates faster implementation

using a modular architecture. It wires together several different

'components' in a

file'

[image:29.517.47.419.44.273.2]

wiring together of_components,

BlinkM,

LedsC and SingleTimerwith Main for

building

an application that toggles the Leds _every clock interrupt using the Timer. This

applicationhas been built

by

theTinyOS developers andisavailable for TinyOSusers.

Figure3.3: ComponentswiredtogethertobuildtheBlinkapplication_[25]

TinyOS implements an event-driven executionmodel, which enablesfine-grained power

management and at thesame time allowsthe_{necessary scheduling}

flexibility

requiredin

WSN application,

[tinyos.net] Long

procedures are scheduled to be executed in series

and are called tasks. Interrupts (or _events) can preempt the scheduled tasks.

Lengthy

operationsmustbe spreadovermultiple_tasks, suchthateachtaskis keptshort enoughto

ensure low task latency. It performs split-phase operations

[26]

allow for concurrency

withlow memoryoverheadsincontrastto athread-based_concurrencymodel. Split-phase

operation: Uses

'commands'

to request the execution of a certain operation, and returns

immediately

to execute the scheduled sequential tasks. The completion oftherequested

operation will then be signaled

by

an 'event'. Such a_no-blocking operation results in

low-memory

resource overhead. Example:

'send'

command requests the _sending of

packets. Once thepacketshave been transmitted,the

'sendDone'

3.2.2 NesC:

TinyOS as well as customized applicationonMICA2 are written in NesC programming

language. It supports a _programming model that allows component-based _programming,

event-driven execution

thereby

_supporting a flexible _concurrency model. With nesC,

performing program optimization and compile-time data race

detection,

it reduces the

memoryutilizationand alsohelps detectpotentialbugs earlyon[26].

NesC is like an extensionto _{C. The programming}ofthe low level abstraction is done in

C,

but nesC has additional features

-the low level abstractions (written in

C)

are

organized as

functions,

which are then organized as components and allow concurrent

operation.

There aretwo types of components:

>

Modules,

whichdescribethecomponents_{using code,} inthreeprogramblocks:

events, commands andtasks and

>

Configuration,

thatwiresthedifferentcomponents, tobuildanapplication.

However,

thesplit-phase operation ofTinyOS makesit difficult toprograminnesC [26].

The TinyOS developers have provided the users with _many programmed low-level

components. These could be used to build custom applications,

by

simply wiring the

4. Programmable

System-on-Chip

(PSoC)

TM

4.1 PSoc

Hardware

Framework:

The PSoC

Family

supplied

by

Cypress,

consists ofan _arrayofconfigurable _analog and

digital blocks (highlighted in yellow in figure

4.1)

with a central micro-processor. It is

very useful in

building

customized designs on one chip. Figure 4.1 shows the block diagramofaPSoC

device,

part-number: CY8C274x3.

PSoC CORE

Systemsus

rt5 Port-4 '_PortaPort2

_M

Global Digital interconnect

Portl ' _PortC Analog

Drivers

M

Global _Analog Interconnect SRAM

256 Bytes

Interrupt Controller

SROM Rash 16K

CPU Core_(M8C) Sleep and Watchdog

MultipleClockSources

(IncludesIMO, ILO, PLL,and_ECO)

f

?.?.?..?

T

T

Digital Clocks

Multiply

Accura Dscirraior |2C

PORand LVD System Resets

Ircemal

Voltage Ref.

SwItch Mxle

Pump

[image:32.517.109.412.239.655.2]

As can be seen from the figure

4.1,

PSoC architecture has a central processor, Data

SRAM,

Flash program _memory, configurable _analog and digital

blocks,

programmable

I/O_ports,clock generator and someother system resources.

The M8C microprocessor is apowerfulprocessorwith an 8-bit Harvard architecture and

can operate on speeds as highas 24MHz. It utilizes an Interrupt Controllerthatprovides

interruptmanagementfor 17 interruptvectors.

Sleep

and

Watchdog

timeris also utilized

toprovidetimedand protected program execution.

PSoC devices have multiple clock _sources, clock dividers and multipliers that provide

flexibleclock generationto the microcontroller as well asthe_analoganddigital blocks. It

has a24MHz Internal Main Oscillator

(IMO)

and a 32KHz Internal Low Speed Oscillator

(ILO).

Also,

a 32.768KHz external crystal oscillator _along with a PLL (Phased Lock

Loop)

canbeusedto generate crystal-accurate clock.

The general purpose input/output pins

(GPIO)

allow great

flexibility

for external

interfacing,

because each pin's drivemode can be selected from eightoptions andit also

has an optiontogenerate aninterrupt incaseof predefined eventsat apin.

The PSoC

family

has different device groups basedon the digital and _analog pin _count,

the program memory, data memory and the number of configurable digital and _analog

PSoC Device

Group

a E o *> OJ 5

t

o

1

CB Q to -: o o ffl

5

a e

f

<

1

a o o < E 3 O o > < _____

S

I5 < S < K (rt <*-O c < m es u.

s

3 O <

CY8C29X66 64 4 16 12 4 4 12 2KB 32KB

CY8C27X43 44 2 8 12 4 4 12 256 Bytes 16KB

CY8C24X94 50 4 48 2 2 6 1 KB 16KB

CY8C24X23 24 4 12 2 2 6 256 Bytes 4KB

CY8C24X23A 24 4 12 2 2 6 256 Bytes 4KB

CY8C22X13 16 4 8 1 1 3 256 Bytes 2KB

CY8C21X34 28 4 28 0 2 4*

512 Bytes 8KB

CY8C21X23 16 4 8 0 2 4*

256 Bytes 4KB

*

[image:34.517.80.439.40.310.2]

Limited _analogfunctionality.

Table 4.1: Available PSoC Devicegroups._[27]

These device groups are further divided into different parts

depending

on the package

type andpin count. Inour work we usePSoC chip

CY8C27443,

28pinPDIPpackage, it

has 8 configurable digital blocks and 12 configurable _{analog blocks. It has 256 bytes} of

RAM and 16KB of program memory. The range of_supplyvoltage for PSoC varies from

3.0Vto5.25V. The digitaland _{analog blocks}withinthePSoC device hasthesame_supply

voltage range.

4.1.1 Digital Blocks:

The block diagram ofthe digital block is shown in Figure 4.2 Each block has a 8-bit

resource, therefore it can be combined with the other blocks to build

16,

24 or 32 bit

peripheralblock. Forexample, a

16,

24,

32 bittimeror acounter. Thedifferentperipheral

16-32 bit Pulse WidthModulators (withandwithoutdead

bands)

8, 16,

24or32bit Counter

8,

16,

24 or32 bit Timers

SerialCommunicationblocks such as

UART, I2C,

SPI

A 8to 32 bitCRC_{(cyclic redundancy check)} checker/generator

Ora pseudo-random sequence generator

Theseblocks canbe placed

by

theuserin the desired

blocks,

thesignals fromthe blocks

can alsobe routedto theGPIO.

Pen;

t

&h

OsgitaiClccks ToSystemBus _ToAr>a!og

Fro-mCce _A System

*

DIGITAL SYSTEM

Digital_{PSoCBIockArray}

Row0

ZZZJ

T _

-SSoo]

loeec IIixaiil

focsis]

t_x__t_zu

/-*

\%

f 9

Row 1

I

I

E7~3

Jr<-~

iSSIO

TZ

D6B11 DC51S

TL*

v siep:o}

eiopj

3C'Cs0ala

[image:35.517.130.398.269.557.2]

mstioosweet 3ocpo;

Figure 4.2: Block diagramoftheconfigurabledigital block_[27]

4.1.2

Analog

Blocks:

The

Analog

blocks are what makesthe_{PSoC very}useful inout application. CY8C27443

internally

are _{specifically designed}

keeping

the common embedded

systems'

design

requirements. _{These analog blocks} can be applied to design customized functions. The

block diagramoftheconfigurable_{analog blocks is} showninfigure4.3.

=3R-=313; =M1

_r<h

P2I3J*_*

P2I1J

*-=c[i;

>D-=<w

<j^3"=cp:

R2J1

P2R

ArrayfnputConfiguration

E=

1_f

Eoc&Array

I

-:C

i,c&:cVi Iacb:i k

JTackT]

j-|ac3os|

]__3

-E

L.^tccff-F]

-r~~2 ]2--?;\:;_

"jASQ13[h.

L.

I_. Ensertace

to

Ci^stal System P.*-T_d

-AnalogHeference

Reference Generators

AGM3!n

Bit'

[image:36.517.146.365.124.467.2]

MEC Jnterfac*{AddressBus. Cata Bus. Etc)

Figure 4.3: Block diagramoftheconfigurableanalogsystem_[27]

It sometimes needs a little bit ofexperience and some _creativity to be able to use the

provided functions to build a required customized application. Some of the common

PSoC functions thatcanbe build_{using theanalog blocks} arelistedbelow:

Variety

of

Analog

to Digital

Converters,

such as

Delta-Sigma,

Incremental,

SuccessiveApproximation etcwithaselectable resolutionof

Analog

Filters:

band-pass,

low-pass,

notch

ProgrammableGain Amplifierthatcanbeprogrammed_up to48times

Instrumentationamplifier with a selectable gain_upto93 times.

Comparators

Digital to

Analog

Converters

Modulators

4.2

Programming

Environment:

The PSoC design software needs to be different from those used for programming

traditional fixed function microprocessor,because ofthe configurable _analog and digital

hardware blocks. The PSoC Designer Integrated Development Environment

(IDE)

developed

by

Cypress Microsystems is an innovative softwaredevelopmentenvironment

for PSoC. It is aGUI-based design suite that simplifies the

designing

ofthe configurable

blocks,

provides the libraries for

developing

customized application _code, provides

advanced

debugging

tools _usingan emulator and supports _{the programming}ofthePSoC

chip.

Figure A. 1

(Appendix)

shows the block level diagram ofthe programmable _analog as

well as digital blocks along with

interconnects,

which can be programmed as per the

desiredroutingofthesignals.

The PSoC application code is developed in threemain stages which is shown in figure

Device Editor

User Mxtule Selection

Raoemart

am

Raiarneter

-Isrtion

Source Code Generator

Generate Application

Application Editor

RrojecJ Manager

Source Cede Editor

Build Manager

Busld All

Debugger

Interface

;oICE

Sterne Inspector

Bert & Ereahpoin:

[image:38.517.147.367.42.347.2]

Manager

Figure 4.4: User ModuleandSourcecodedevelopment flow in PSoC Designer _[27]

The Device Editor allows theuserto choose the functionalcomponent (e.g. ADC/ filter/

timer/ counter _{etc) for} each of the _analog or digital blocks (shown in figure A.l in

appendix). Theuserhas an optionto placethese components withinthe permittedblocks

and route the signals

by

_making or

breaking

the programmable interconnects or

by

programming the multiplexers as per the requirement of the design. The device editor

also allowstheuserto set theparameters

(user-defined-registers)

ofthe _analoganddigital

component. In PSoC Designer

IDE,

the standard components have libraries ofpre-built

and pre-tested hardware functions. The _{corresponding} libraries of the selected

components are generated and added to the projects in the device editor before _moving

Application

Editor

The application editorallows theusertowrite thecode eitherin C language or_assembly

language. _{The analog} and digital blocks must be initialized in the code _using the

generated component libraries. It also gives access to the interrupt service routine. The

code is then assembled/ _compiled, linked and builtwithout _anyerrors _{before moving} to

thedebuggertoevaluatethedesignon an emulator.

Debugger

Debugging

is the _{last step in} the development process of PSoC. PSoC designer IDE

provides an In-Circuit-Emulator

(ICE),

which allows

debugging

at the _{full operating}

speedofPSoC. A HEX file is downloadedonto the ICE andit has advanced

debugging

features inaddition_{to the single-step,} breakpoints and watch-variables. It allows the user

to define complex breakpoint events and also alarge trace buffers that allow the user to

5.

Interface

Design

This chapterdiscusses the implementation ofthe interfacebetween MICA2 andPSoC in

detail. It focuses on the _{hardware setup} and _programming of the PSoC and MICA2

required fortheimplementationofan

interface

betweenthem.

MICA2 and

PSoC,

both support _{Universal Asynchronous Receive/Transmit}

(UART)

serialcommunication. MICA2supports abaud rateof57600bitspersecond. The UART

pins in the MICA2 mote is brought to the 51 pin connector.

However,

since this is a

development phase, direct soldering on the machine soldered components of MICA2

sensor node(called

'mote')

isavoided. Insteadabreakout board isused, whichbringsout

the signals at the 51 pin connector. The breakout

board,

called the Serial

Gateway

MEB510CA (figure

5.1)

is made available

by

Crossbow

Technology

Inc. The serial

gateway provides a RS232

interface,

_converting the UART signals to _{RS232 using}

MAX-3223I chip. It has a 9-pin RS232 connector. This board is generally used for

interfacing

themote withthecomputer at thebase stationor for programming_{the motes,}

using itson-boardprocessor.

Figure5.1(a) Figure5.1(b)

5.1

Programming

PSoC

to support

UART

serial communication.

For the PSoC to be interfacedwith

MICA2,

its digital blocks need to be programmed to

support UART communication at a baud rate of 57600 bps. This section describes in

detail the _programming of digital as well as _{analog blocks} ofPSoC for _{sampling the}

sensor signal and then

transmitting

it _serially to MICA2. Figure 5.2 illustrates the

peripheralblocksrequiredtobeprogrammedin PSoC.

> Sensed analog signal w Programmable Gain Amplifier (Gain=₁₎ Amplified analog signal w Analog toDigital Converter

ROM SENSOR >

JARTreceive signal

>

Digitalequivalent of sampledanalog

signal

Microprocessor

t k _Datare viaUART cotnmun ceived serial cation > Data to using Ui cornmur r besent Rlserial ication FROM MICA2 UART Receive block UART Transmit block UART transmit signal TOMICA2

UARTfromRS232

-\w after_converting toRS232

[image:41.517.39.468.240.538.2]

P SoC

Figure 5.2: Block diagram showingthedigital(blue/ belowthe_MCU)and_{analog (green/}abovethe

5.1.

1:

Amplifier.

The Programmable Gain Amplifier

(PGA)

uses _{only 1} peripheral

(analog)

block. It is

used toprovide highinputimpedanceto the transducer. Figure 5.3 showsthePGAblock

diagraminthePSoC.

Output

CT_BLOCK

AGND

Vss SC_BLOCK 1

[image:42.517.161.359.155.313.2]

Reference

//f

Figure 5.3: PGA Block diagram in PSoC _[30]

In our design thePGAis programmed for unitygain, the referenceis selected as AGND

and the _{analog bus is disabled. For}a_unitygain, the outputMUX is connected to the

top

ofthe resistor _string and feedback to the

inverting

input is connected to theresistortap.

ThetransferfunctionofthePGAisthereforeas follows:

f

R,

The Device Editor ofthe _{PSoC automatically}programs the appropriate resistor values

depending

ontheuser-definedgainvalue.

5.1.2:

Analog

toDigital Converter

(ADC)

The PSoC has a number ofdifferent ADC's to select from

depending

on the required

peripheral_analogand digital blocksavailable. It offersIncremental Type

(algorithmically

equivalent to a Dual Slope _{type), Successive Approximation} as well as Delta-Sigma

ADC's.

SC PSoC Block

M

Ref+-t

Ref-

-I

I

. ACAP=16

A.

FCAP=₃₂

\

o,'Reset

r

-o

DataCiock

-Generator

-o,

-*,

Enabe Int

8Bit Counter

CPU

-t Data

Bus

Out

16 Bit PWM

[image:43.517.90.438.125.337.2]

h CPU

Figure 5.4: Simplified Block diagramoftheIncremental ADC in PSoC _[31]

In our design aVariable Resolution Incremental ADC has been selected, because ofits

flexibility

to

finely

tune the sample rate and changetheresolution as perthe application

requirement

during

the development stage. It uses

integrator,

_comparator, reference

signals, counter and a pulse width modulator (PWM). In our design the ADC has been

programmed for a resolution of 11 bits and the data clock 2.4MHz. It uses 1 analog

peripheralblockand3 digitalperipheralblocks for 8 bit counterand 16 bit PWM.

The algorithm is similar to that ofa dual-slope

ADC,

_whereby an unknown voltage is

integrated over a fixed amount of time and then a known reference signal is

the

integrate

time is kept track _using the PWM. The PWM also gates the clock to the

counter.

5.1.3: UART

Receive/ Transmit Blocks:

UART Receive/ Transmit blocksuse2digitalperipheral

blocks,

onefor receivingandthe

other for transmitting. It is required to be programmed for a baud rate of 57600 for

interfacing

with MICA2. The input clock to the UART blocks needs to be 8 times the

required baud rate. Hence the clock is 460.8 KHz. The transmit interrupt request is

enabled, therefore once atransmit registeris empty the microcontrolleris interrupted to

sendmore data.

1% Cetirol/Status Register

Clock

Input

Tx3uffr

Enable

Tst 8isfe;

p\ TKir.

I1 -^ _Rtques:

ntEr3b"a

't Compete

r

Tx Shift Reasier

J*

"Output

Rx Shift

> Register

Enable

RxData

Rx BufV

RX Ac:ive :_'3m ing

Erro'

Parity Error

Overrun

Error

RX RegisterFull

1 \ Ry in:

|

\

* Request [image:44.517.54.468.314.520.2]

Rx ControlJStatws Register IntEnable

Figure 5.5: Internal Block DiagramoftheUART ReceiveandTransmitblocks.[32]

As seen from figure

5.5,

the transmit and receive, control and status registers are

different. Since the data comes in as a bit _{stream, the} data is accumulated in a shift

5.1.4: The Device

Editor

Placing

and Routing:

Figure 5.6 showstheDevice Editor

(DE)

after_programming theperipheral blocks onthe

PSoC. The UART

blocks,

PGAandtheADCare placed intheDE. The interconnects are

programmed to routethe signals correctly. The global resources and the user-parameters

for each oftheprogrammed user modules are also defined in the DE. In figure 5.6 PGA

block (is placed _{in green)} receives the _analog signal from the sensor. The output ofthe

PGA is routed theinput ofthe ADCblocks (inred). The UART receive/transmit signals

from the UART blocks (in

blue)

are routed to the port pins to transmit to MCU in the

node. Moredescriptiononthesecanbe found in [24].

opo ci se c.

ftJ W<TO

KCXI-I

&'>'' o* t*^- C

R

us

K>l;Oj until

k!

e

...i

?

[image:45.517.52.449.287.650.2]

5.1.5: Application

Editor (AE):

The libraries ofthe peripheral components placedin the DE are generated and available

toview and editintheAE. Each oftheuserprogrammedperipheral componentsmustbe

initializedintheapplication code.

Using

the

library

functions,

the_{ADC sampling is} setsuchthatitwill_continuouslysample

the

incoming

signal at its pre-defined (in

DE)

_samplingrate. Each sampleis read into an

integer (2

bytes)

variable,sincetheADC resolutionis 1 1 bits. Thisvariable valueisthen

transmitted_{serially using}theUART

library

functions.

5.1.6: The Pin Diagram ofthePSoC:

After _programming of the peripheral

blocks,

_routing the signals to the port pins and

initializing

theblocks inthe

AE,

thepindiagramofthePSoC is asshownin figure 5.7

Port_.0_7

Port_0_5

Port _0.3 AnakKjCalumnJnputMUX_0

Analogsignalf _{Port 2 7} fromsensor I

I Port_2_S

Port_2_3

Port 2 1

Port_W

Port_l_S

Port_1_3

Port 1 1

1_P0|7| 2P0|5| 3P0|3] 4P0l1| 5P2|7| 6P2|S| "W

7P2|3| CYBC27443BPDIF*2 SP2|1| 21

9SMP 20

10P1(7| 19

11P1[5] 18

12P1|3] 17

13P1(1] ,a

14VSS '-'

VOL) P0|6| P0|4] P0|2| P0[0| P2|6| P2[4| P2[2| P2|0| XRES Pl|6| P)(4) P1[2| P1[0| JPort_0_6 Ipnrt (14

3port_0_2 UART Transmit

IPortOJ) UARTReceK-8

ZUPort_2_6

]Port 2 4

3Port_2_2

]Port 2 0

jPortJJi IZ]Poi1_1_4 ]Port__12 ZUPot1_l Std CPU Global In Glonal Out AnalogIn AnalogOut

Figure 5.7: Pin DiagramofPSoC after_programmingtheperipheralblocks.

5.2.

UART to

RS232

Conversion at

PSoC

end

The UART voltage signals from the PSoC chip vary between 0 to 5 volts as per the

12V to -12V. RS 232 is amore reliable serial communicationprotocol; because it has a

[image:47.517.46.476.207.454.2]

greater noise margin.

Figure 5.8 showstheschematicdiagramfortheconversionofUARTsignals atthePSoC

toRS232requiredfor

interfacing

withMICA2. ItusesMAX233 IC

[33],

whichperforms

thelevel conversion.Figure 5.9 shows asnapshot ofMICA2interfacedwithPSoC

iSVIfPIIT i-rom Senaor (28 VDD Port0[1] Input to PGA

CY8C27443 PDIP GMD Port0[2] UART TX Port0[0] UARTRX 25 24 wVIM'IIT LtljiF 2 TTLCMOS _ 1 OIJPJTS {_ 12m 14-IHTfflW. raosurrtY

tl-rTFPNAr+1W Hj9

powersupply

iy{

_ Tim Rlmii ti<m r^ v-Vcc MAX&S GIB ac rim.T R&t H2l C2-. WU VI- C2-Ts orpins 4 RS-232 iwrs 1? 11 1121

3

m: txSaia S \oooo >S1"* 1/ 6 9 DB9male connector

[image:48.517.94.436.42.301.2]

Figure 5.9: SnapshotofMICA2 interfacedwithPSoC.

5.3

TOS Message

Structure:

TinyOS has amessage structure that must be followed while _{communicating wirelessly}

or _seriallywith the motes. Just sending a randombyteofdatawill not beunderstood

by

MICA2 and will therefore be rejected.

Hence,

in order to interface PSoC with MICA2

serially, itis important tounderstand the TinyOS message structure and

thereby

transmit

thedata fromthePSoC inaccordance withit.

5.3.1 Packets:

TinyOS messages are sent in 'packets'. A raw packet has 2 synchronization

bytes,

the

packet type and the TOS message. The contents of araw packet are illustrated in table

5.1. The frame synchronization byte

(0x7E)

marks the start and end of the _packet;

not an

'acknowledgement

is required'

to be sent back after

having

received the packet

correctlyor whetherthepacketis an

'acknowledgement'

being

sentbackto thesender of

the original packet. For our

design,

the packet type sent from the PSoC to MICA2 is a

user _packet, with no acknowledge required. It has been highlighted in table 5.1. The

payload data contains the TinyOS message; it is in this message that the sampled data

willbetransmitted.TheTinyOSmessagestructurehas been discussed inthenext section.

SYKC_BYTS Packet Type

Payload Laz& 5YNC_3YTE

0 1 2.. .n-i n

Byte # Field Description

0 Packet framesynch

byte

Always0x7E

1 PacketType Theie are5 knownpackettypes:

P_PACKET_NO_ACK (0x4₂₎- User_packet

withnoACKrequired.

P_PACKET_ACK(0x4₁₎- User_packet.ACK

required.Includesaprefixbyte.Receivermust send aP_ACKresponse with prefixbyteas contests.

P_ACK (0x40)- The_ACK

responsetoa PJPACKET_ACKpacket,includestheprefix byteasitscontents.

P_L"NKNOWN_(OxFF)

-Anunknown packet tvpe.

2...n-l Payload Data Inmost cases willbeaTinyOSMessageof_varying

length,which described below.

[image:49.517.59.460.205.469.2]

n SYNC BYTE Always Jx~Z

Table 5.1: Packet Structure in TOS Message Structure[34]

5.3.2 TOS Message Structure:

The TOS message structure, illustrated in table

5.2,

has 5 bytes of

header,

followed

by

data bytes (also called payload

data)

and ends with the 2 bytes ofCRC. The number of

Theheader consistsof5 bytes: thefirst 2bytes havethe destination address

-inour case

itwill be the UART address. The UART addresshas been set to 0x007E. The nextbyte

indicates the message type

-since our message is

being

transmitted via

UART,

the

messagetype is AMTYPE_XUART. Then follows the

Group

ID for motes of one _group

to

identify

each otherin an environment with multiple sensor nodesofdifferentnetworks

are present. Sincewe do nothave multiple motesor networks _present;we use the default

group

id,

0x7d. Next

byte,

the data length indicatesthenumber ofdata bytes that follow

Address Message

Type

Sroup

Le^cr"]*'

Ca-a CRC

0 I 2 2 3 4 5. . .r.-2 r.-l ! n

Byte# Field

Description

0-1 Message Address Oneof3possible valuetypes:

* Broadcast Address_(OxFFFF)

-messagetoall

nodes.

UART Address₍5x0 07e)-_messagefroma

nodeto the_gatewayserial pert.All

incoming

messages willhavethisaddress.

Node Address

-theuniqueEDof a nodeto

receivemessage.

2 Message Type ActiveMessage

(AM)

uniqueidentifier forthe typeof

messageit is.

Typically

each application willhaveits

own nuroazetvee.Examplesinclude:

? _{AMTYPE XUART} =_OxOA AMTYPE_MHOP_DEBUG~0xO3 ? _{AMTYPE SURGE} MSG 0x1 1

AMTYPE XSENSOR -_0x32 ? AMTYPE_XMULTIHOP -0x33

AMTYPE MHOP MSG -_OxFA

3

Group

ID Unique identifiedforthe_groupofmotes_{participating in}

thenetwork.Thedefaultvalueis 125 (Cx"?d).

Only

motes withthesame_{group id}willtalktoeach other.

4 Data Length Thelength

(T)

mbytesofthedatapayload.This doesnot

includetheCRCcrframesvnckbytes.

5...n-2 Payload data Theactualmessagecontent.The dataresides atbyte 5

throughbyte 5plusthelengthofthedata (Ifromabove).

Thedatawillbespecificto themessagetype.Specific

messagetypesarediscussed inthenext section.

n-l,a CRC Twobytecodethatensuresthe

integrity

ofthemessage.

TheCRCincludesthePacket Typeplustheentire unescapedTinyOSmessage. A discussiononhosvthe

[image:51.517.64.457.43.458.2]

CRC iscomputedisincludedintheAppendix.

Table 5.2: Field description inpackets ofTOS Message Structure. Source: [34].

The Payload data can _{vary between 1} and 26 bytes. In our design we

keep

the payload

dataconstant at26. The payloadis where our sampled datais added. The last 2 bytesof

the TOS message structure are the CRC

bytes,

used for checking the

integrity

ofthe

received signalatthereceiver. The C-code for calculatingtheCRCofthepacketis found in the

[octave-tech] document,

which explains the TOS message structure in further

5.3.3 PSoC

and TinyOS Message

Structure:

Therawdatapacketsto betransmitted from PSoCto _{MICA2 using}UART look asshown

in figure 5.10. It show three raw data packets _serially transmitted from the PSoC to

MICA2. The data has to be sent in a little-endian format. The synchronization byte

(0x7E),

packet type

(0x42),

UART address (0x007E = _{7D 5E}

00,

because of_escaping

byte),

Message type -UART

(0A)

and

Group

ID

(7D)

are highlighted in yellow. The

payloaddata highlighted in

blue,

_green,pinkand _greyare arrangedinanOscope message

structure. This structure is used

by

Oscilloscope,

which is ajava-based program that is

usedto

display

the sampleddataat thebase station. The Sourcemoteindicates themotes

ID,

incase there exists more than 1 mote

transmitting

data in the n/w. The sample

numbers are kept track of and the last sample number is sent out with each packet.

Channel indicates the ADC channel, incase of more than 1 element is

being

sensed at a

mote. The dark-green highlighted bytesaretheCRC bytes.

TE 42 7D51 00 0A 7D SDIA iffiBin1^1 13 &1 1301 1201 13 01 13 011301 13 01 14 01 13 01 _Ml7E

7E 42 7D 5E 00 0A 7D 5D IA 01 00 W\1 5 0 1 16 01 15 01 15 01 16 01 15 0115 01 1501 15 01 15 01 f__73

7E 42 7D 5E 00 OA 7D 5T> IA OMHIH13 01 1201 1201 1201 12 01 12 0112 01 1201 1101 1201__l7E

Standardpackets:Sync bytes. Packettype,UARTaddress.GroupID,=ofdata bytes

OscopeMessage Structure:

&_tHHH8% Oxoooi :0x079Z

Data

Figure 5.10: Example Raw Data PacketstobesenttoMICA2

Figure 5.11 describes the program flow ofPSoC in order to send the data in the TOS

message structure described above. Since the data payload (last sampled number and