CONTROL SYSTEM LABORATORY

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DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 1

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ABORATORY

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EPARTMENT OF

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NIVERSITY OF

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1. OBJECTIVE

To demonstrate the concept of Lead-Lag Compensation.

2. COMPONENTS & EQUIPMENT

PC with MATLAB and Simulink toolbox installed.

3. BACKGROUND

Lead–lag compensators (e.g. PID controllers, etc.) influence disciplines as varied as robotics, satellite control, automobile diagnostics, and laser frequency stabilization.

Both lead compensators and lag compensators introduce a pole-zero pair into the open loop transfer function, which can be written in the Laplace domain as

𝑌(𝑠) 𝑋(𝑠)=

𝑠 − 𝑧

𝑠 − 𝑝 (1)

where X is the input to the compensator, Y is the output, s is the complex Laplace transform variable,

z is the zero frequency and p is the pole frequency. The pole and zero are both typically negative, or left of the zero in the complex plane. In a lead compensator, |𝑧| < |𝑝|, while in a lag compensator |𝑧| > |𝑝|.

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EE370L CONTROL SYSTEM LABORATORY

A lead-lag compensator consists of a lead compensator cascaded with a lag compensator. The overall transfer function can be written as

𝐺_𝑐(𝑠) = 𝑌𝑐(𝑠) 𝑋_𝑐(𝑠)= 𝐴 ∙

(𝑠 − 𝑧₁)(𝑠 − 𝑧₂)

(𝑠 − 𝑝₁)(𝑠 − 𝑝₂) (2)

Typically, |𝑝1| > |𝑧1| > |𝑧2| > |𝑝2|, where 𝑧1 and 𝑝1 are the zero and pole of the lead compensator, 𝑧₂ and 𝑝₂ are the zero and pole of the lag compensator. The lead compensator provides phase lead at high frequencies. This shifts the root locus to the left, which enhances the responsiveness and stability of the system. The lag compensator provides phase lag at low frequencies which reduces the steady state error.

An example is illustrated in the Appendix of this instruction manual.

*Note: The precise locations of the poles and zeros depend on both the desired characteristics of the closed loop response and the characteristics of the system being controlled. However, the pole and zero of the lag compensator should be close together so as not to cause the poles to shift right, which could cause instability or slow convergence. Since their purpose is to affect the low frequency behavior, they should be near the origin.

Design Objectives/Parameters

|𝐺(0)|, 𝑒𝑠𝑠0=

1

1 + |𝐺(0)| DC gain, Steady-state error

𝜔_𝑐, 𝜔_𝑏, 𝜔_𝑚 Gain crossover frequency, Bandwidth, Phase value at 𝜙_𝑚𝑎𝑥 𝑇_𝑟, 𝑇_𝑝, 𝑇_𝑠 Rise time, Peak time, Settling time

𝜙_𝑝 or 𝜙_𝑃𝑀, 𝑀_𝑚 Phase margin, Magnitude value (dB) at 𝜙_𝑚𝑎𝑥 𝑀_𝑝 or %𝑂𝑆 Percentage overshoot

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Figure 2

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4. LAB DELIVERIES

PRELAB:

1. Study the knowledge of lead-lag compensator, part of which is introduced in the previous section.

• An example is illustrated in the Appendix of this instruction manual.

2. Use MATLAB to depict the following uncompensated transfer function given below.

𝐺(𝑠)= 9.33𝑠 + 176

𝑠4_{+ 6.03𝑠}3_{+ 33.2𝑠}2_{+ 11.7𝑠 + 0.00442} 1) Draw the Bode plot.

2) Plot |𝐻(𝑗𝜔)| and the closed loop step response for unity gain feedback systems. 3) From 1) and 2), record predicted values of 𝜔_𝑐, 𝜙_𝑝, 𝑇_𝑠, 𝑇_𝑟, 𝑇_𝑝, 𝑀_𝑝, 𝜔_𝑚, 𝜔_𝑏 and 𝑀_𝑚, for

closed-loop system H, if applicable.

4) Plot achievable values for 𝜙𝑝′ vs. 𝜔𝑐′ for arbitrary gain compensation 𝐾 = 1, 2, … 50. (Use “semilogx” command in MATLAB).

5) From 4), determine 𝜔_𝑐′, 𝜙_𝑝′ and K so that gain compensated closed loop systems meets the following specifications.

𝑒𝑠𝑠₀ ≤ 0.01 𝜔_𝑐′ ≥ 2 × 105 rad/s

𝜙_𝑝′ _{≥ 60°} 6) Construct Bode plots corresponding to 𝐾 ∙ 𝐺

7) Plot |𝐻(𝑗𝜔)| and closed-loop step response of the new compensated closed loop systems.

8) From 6) and 7), repeat 3)

9) Design a lead-lag compensator based on Figure 7 or Figure 8. Let 𝑅₂ = 510Ω (to minimize interaction of the compensator with input and output impedance of the amplifier). Find the value of 𝑅₁ for 𝐾 = 5.

10)Plot achievable values for 𝜙_𝑝′_{vs. 𝜔}

𝑐′ for lead-lag compensation.

11)Based on your graph, determine 𝜙_𝑝′, 𝜔_𝑐′, 𝑝₁, 𝑝₂, 𝑧₁ and 𝑧₂ so that the new closed-loop system 𝐻 = 𝐺_𝑐 ∙ 𝐺 with lead-lag compensation achieves the specifications in 5). 12)Bode plot corresponding to the new H.

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LAB EXPERIMENTS:

1. Base on Prelab 2, complete the following tasks.

1) Construct power amplifier in a unity gain feedback;

2) Apply a square wave input and record 𝑇_𝑟, 𝑇_𝑠, 𝑇_𝑝, 𝑀_𝑝 and 𝑒𝑠𝑠₀; 3) Apply sinusoidal input and record 𝜔_𝑚, 𝜔_𝑏 and 𝑀_𝑚;

4) Repeat 2) and 3) for gain compensated network. 5) Repeat 2) and 3) for lead-lag compensated network.

POSTLAB REPORT:

Include the following elements in the report document:

Section Element

1 Theory of operation

Include a brief description of every element and phenomenon that appear during the experiments.

2 Prelab report

1. MATLAB codes and figures for Prelab 2

3

Results of the experiments

Experiments Experiment Results

1 MATLAB code, Simulink model and simulation results for Experiment 1.

4

Answer the questions

Questions Questions

1 What can you conclude from lead-lag compensator?

5

Conclusions

Write down your conclusions, things learned, problems encountered during the lab and how they were solved, etc.

6

Images

Paste images (e.g. scratches, drafts, screenshots, photos, etc.) in Postlab report document (only .docx, .doc or .pdf format is accepted). If the sizes of images are too large, convert them to jpg/jpeg format first, and then paste them in the document.

Attachments (If needed)

Zip your projects. Send through WebCampus as attachments, or provide link to the zip file on Google Drive / Dropbox, etc.

5. REFERENCES & ACKNOWLEDGEMENT

1. Norman S. Nise, “Control Systems Engineering”, 7th Ed.

2. https://en.wikipedia.org/wiki/Lead%E2%80%93lag_compensator

I appreciate the help from faculty members, TAs and students who provide valuable feedback during the composing of this instruction manual.

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Appendix

Operational Amplifier Model:

In this experiment, you will be using the LM12 power op amp. A close approximation to the actual response of the LM12 is given by the transfer function

𝐺(𝑠) = 9.33 × 10 18_{𝑠 + 1.76 × 10}26 (𝑠 + 377)(𝑠 + 3.77 × 105_{)(𝑠 + (2.83 + 𝑗4.81) × 10}6_{)(𝑠 + (2.83 − 𝑗4.81) × 10}6₎ = 9.33 × 10 18_{𝑠 + 1.76 × 10}26 𝑠4_{+ 6.03 × 10}6_𝑠3_{+ 3.32 × 10}13_𝑠2_{+ 1.17 × 10}19_{𝑠 + 4.42 × 10}21 (3)

𝐺(𝑠) has a DC gain of 92dB, a zero at 300 KHz, and poles at 60Hz, 60 KHz, and (450 ± j765) KHz. Actual values of these parameters vary somewhat from chip to chip, but the mathematical model is still accurate enough to obtain good results.

For the sake of numerical stability and convenience, we will perform a frequency scaling by a factor of 106, and 𝐺(𝑠) becomes

𝐺(𝑠)= 9.33𝑠 + 176

𝑠4_{+ 6.03𝑠}3_{+ 33.2𝑠}2_{+ 11.7 + 0.00442} (4)

As a result of frequency scaling, all frequencies (e.g. those appearing on Bode plots) must be read as “Mrad/sec”, rather than “rad/sec”, and “MHz”, rather than “Hz”. Similarly, values of time must now be read as “μsec”, rather than “sec”.

Phase Margin (PM) and Gain Crossover Frequency (GX):

It is useful to refer to the Bode plots for 𝐺(𝑠) to define the PM and GX:

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The gain crossover frequency of G is the frequency 𝜔_𝑐, where |𝐺(𝑗𝜔𝑐)| = 1. On the magnitude plot shown above, 𝜔_𝑐 corresponds to the location of the 0dB axis crossing. PM is the difference of the phase angle from 180 degree at the gain crossing frequency.

Let us investigate a simple unity gain feedback systems:

Figure 5

With 𝐾 = 1, resulting closed loop transfer function is as follows: 𝐻 = 𝐺

1 + 𝐺 (5)

Since |𝐺| ≥ 1 for all 𝜔 ≤ 𝜔_𝑐, we have |𝐻| = | 𝐺 1 + 𝐺| ≥ |𝐺| 1 + |𝐺|≥ 1 2 (6)

Thus, closed loop bandwidth 𝜔_𝑏≥ 𝜔_𝑐. Phase of the systems is given as:

∠𝜙𝑝 = ∠(𝑗𝜔𝑐) + 180° (7)

A closed-loop transfer function is BIBO stable if and only if 𝜙_𝑝 > 0. Besides, increasing 𝜙_𝑝 tends to move poles of the closed-loop system further to the left in the complex plane, increasing damping. The LM12 has phase margin 𝜙𝑝 = 15°. Thus, the Op Amp alone is unity gain stable.

Phase margin and gain crossover frequency are also closely related to the closed-loop performance specifications. For example, if 𝜔_𝑐 is large, so is 𝜔_𝑏; thus, signals with substantial high frequency components tend to pass through the system un-attenuated. Large 𝜔_𝑏 also tends to give large 𝜔_𝑚. In terms of the step response, large 𝜔_𝑏 implies that 𝑇_𝑟 and 𝑇_𝑝 are small. If 𝜙_𝑝 is large, the closed-loop system is heavily damped, which leads values of 𝑀_𝑝 and 𝑀_𝑚 close to unity. Generally, a phase margin of 60° is considered good; smaller 𝜙_𝑝 tends to result in oscillatory and overshoot phenomena in the closed-loop system response. Settling time 𝑇𝑠 is more closely related to the compensation scheme used, rather than to 𝜙_𝑝 and 𝜔_𝑐, since it depends most heavily on the location of the closed-loop pole with the smallest real part.

Another parameter of interest is DC gain, which sets the steady state settling error. Steady state error and gain relationship is shown below:

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𝑒𝑠𝑠₀ = 1

1 + |𝐺(0)| (8)

As seen from above, large DC gain yields small steady state error. Excluding 𝑇_𝑠, closed loop performance parameters fall into three categories:

|𝐺(0)|, 1 𝑒𝑠𝑠₀ 𝜔_𝑐, 𝜔_𝑏, 𝜔_𝑚, 1 𝑇_𝑟, 1 𝑇_𝑝 𝜙_𝑝, 1 𝑀_𝑝, 1 𝑀_𝑚 Ideally, we would like |𝐺(0)|, 𝜔_𝑐 and 𝜙_𝑝 to be large.

Although we cannot actually change the plant itself, open-loop characteristics can, in effect, be altered by connecting a compensator 𝐺_𝑐 in series with the plant. The series combination 𝐺_𝑐∙ 𝐺 then replaces G in the unity feedback configuration as shown. Our task is to choose 𝐺_𝑐 so that the values |𝐺_𝑐(0)| ∙ |𝐺(0)|, 𝜙_𝑝 and 𝜔_𝑐 (after compensation) are as large as possible.

Gain Compensation:

Setting 𝐺_𝑐 = 𝐾 > 0, the phase plot for 𝐺_𝑐∙ 𝐺 is the same as that for G, but the magnitude plot for 𝐺_𝑐∙ 𝐺 is lowered by 20log (1/𝐾) dB because in Op Amp compensation, K is almost always less than 1. This reduces the crossover frequency to a new value 𝜔0𝑐, increasing the phase margin to a new value 𝜙_0𝑝.

The design strategy for gain compensation is to find a frequency 𝜔_𝑐′_{such that 𝜙}

𝑝′ given by

∠𝜙_𝑝′ _{= ∠(𝑗𝜔}

𝑐′) + 180° (9)

provides sufficient phase margin. K is given by

𝐾 = 1

|𝐺(𝑗𝜔𝑐′)|

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Steady state error of gain compensator is as follows

𝑒𝑠𝑠0 =

1

|𝐺_𝑐(0)𝐺(0)|= 1

𝐾|𝐺(0)| (11)

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Typically, gain compensator is implemented with resistive network to avoid the use of active compensator, which would require additional amplifier complicating the frequency response. A resistive network that implements the gain compensator and implementation of gain compensator for an op-amp circuit are shown below:

Figure 6

For a given K, resistance values may be obtained by solving for R1:

𝑅₁ = (1

𝐾− 1) 𝑅2 (12)

The freedom in choosing R2 may be exploited to avoid interactions between the compensator and the input and output impedances of the amplifier.

Lead-Lag Compensation:

Lead-lag compensation is achieved with the use of following passive network:

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The transfer function of the lead-lag compensator is as follows:

𝐺_𝑐(𝑠) = (𝑠 + 𝜔1)(𝑠 + 𝜔2) 𝑠2_{+ (𝜔} 1+ 𝜔2+ 𝜔3)𝑠 + 𝜔1𝜔2 (13) where 𝜔1 = 1 𝑅₁𝐶₁, 𝜔2 = 1 𝑅₂𝐶₂, 𝜔3 = 1 𝑅₂𝐶₁ From the above equations, we find

𝐴 = 1, 𝑧₁ = 𝜔₁, 𝑧₂ = 𝜔₂, 𝑝1 = 1 2(𝜔1+ 𝜔2+ 𝜔3− √(𝜔1+ 𝜔2+ 𝜔3) 2_{− 4𝜔} 1𝜔2) 𝑝₂ = 1 2(𝜔1+ 𝜔2+ 𝜔3 + √(𝜔1+ 𝜔2+ 𝜔3)2 − 4𝜔1𝜔2) (14)

From the equation above, compensator gain at DC and high frequency equals to unity.

𝐺_𝑐(0) = 𝐺𝑐(∞) = 1 (15)

Furthermore, evaluating 𝐺_𝑐 at DC yields:

𝑝1𝑝2 = 𝑧1𝑧2 (16)

Therefore, only three out of four poles and zeros can be adjusted independently. These constraints are a consequence of using a passive compensator.

The closed-loop circuit with lead-lag compensator is shown below:

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Bode plot of the lead-lag compensator are as follows:

Figure 9

As shown in the phase plot of 𝐺_𝑐, the phase “lags” at lower frequencies and “leads” at higher frequencies. The basic idea in lead-lag design is to choose the lead portion of the compensator (𝑝2 and 𝑧₂) to add phase in the vicinity of the desired gain cross-over frequency 𝜔_𝑐′. The lag portion (𝑝₁ and 𝑧₁) then attenuates the magnitude so that 𝜔_𝑐′_{is actually the crossover frequency. The phase} lag is merely an artifact of the compensator structure and plays no role in achieving the specifications. The new gain crossover frequency is determined by

((𝜔_𝑐′₎2_{+ 𝑧}

12)((𝜔𝑐′)2+ 𝑧22) ((𝜔_𝑐′₎2_{+ 𝑝}

12)((𝜔𝑐′)2+ 𝑝22)

|𝐺(𝑗𝜔𝑐′)|2 = 1 (17)

To simplify the design problem, let us assume 𝑧₁ = 𝑧₂ = 𝜔_𝑐′_{/10. This degrades phase response} at 𝜔𝑐′ only a small amount (less than 6 degree each). Solving for 𝑝1 and 𝑝2 yields

𝑝₂ ≈ (|𝐺(𝑗𝜔_𝑐′_)|2_{− 1)}1/2 𝑝1 = (𝜔_𝑐′₎2 100𝑝2 𝜙𝑝′ ≈ 𝑎𝑟𝑐𝑡𝑎𝑛(𝑝2) + ∠𝐺(𝑗𝜔𝑐′) + 168° (18)

The design process consists of plotting phase equation shown above and choosing a point on the graph that provides acceptable values 𝜔_𝑝′_{and 𝜔}

𝑐′, and calculating 𝑧1, 𝑧2, 𝑝1 and 𝑝2. Resistor and capacitor are derived as follows:

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𝐶₂ = 1 𝑧₂ 1 𝑅₂, 𝑅1 = ( 1 𝑝₁+ 1 𝑝₂− 1 𝑧₁− 1 𝑧₂), 𝐶1 = 1 𝑧₁ 1 𝑅₁

The freedom in choosing 𝑅₂ may again be exploited to avoid interactions between the compensator and the input and output impedances of the amplifier.

*Note: Regardless of the choice of lead-lag compensator, due to Eq. (11), the steady-state error is extremely small. Lead-lag compensation simultaneously achieves small steady-state error, large phase margin, and large gain crossover frequency.