IL2225 Physical Design

IL2225

Physical Design

Nasim Farahini

Outline

l 

Physical Implementation Styles

l 

ASIC physical design Flow

l 

Floor and Power planning

l 

Placement

l 

Clock Tree Synthesis

l 

Routing

l 

Timing Analysis

Overview: Digital Design Flow

System Specification Architectural Design Logic Synthesis

Physical Synthesis

Physical Verification / Sign-off Fabrication

X=(AB*CD)+(A+D)+(A(B+C)) Y=(A(B+C))+AC+D+A(BC+D))

Physical Design

l 

Physical design converts a circuit description into a geometric

description.

l  This description is used to manufacture a chip.

l  Design Objectives

l  Power (dynamic/static)

l  Performance (frequency)

l  Area (cost)

l  Yield (cost)

Physical Design challenges

l 

1-

Design complexity

l  Number of transistors on the chip is increasing

l 

2- Scaling

l  More design rules

l  Manufacturability

l  Variability

l 

3- Productivity

l  Time-to-market

Physical Design Styles

Full-custom design

l  Manual placement of the transistors and wiring.

l  Advantages: Less area, Better performance, Less power

l  Disadvantages: High engineering effort, Long time-to-market,

High development cost

l 

Semi-custom design (standard-cell based)

l  Pre-physically designed commonly used logic cells which are

characterized and stored in standard cell libraries.

l  Used in Electronic Design Automation

l  Routing of inter-cell connections l 

Programmable Logic Devices

Standard-Cell Based Physical Design

l 

Standard cells: layouts of library cells including logic

elements like gates, flip-flops, and ALU functions

Physical Design Flow

A very brief tour of physical design

placement floorplanning floorplanning placement repeater insertion clock tree synthesis P/G network / routing metal fill insertion mask generation gate-level circuit Timing analysis Parasitic extraction Power analysis Signal Integrity

mask mask after OPC Metal Wires Clock Tree

Post Route Analysis Placement

Floor and Power Planning

Metal Fill Insertion

Static Timing Analysis Clock Tree Synthesis

Routing

Post Route Verification

Mask Generation/OPC Parasitic extraction Power Analysis Signal Integrity Gate Level Netlist

Cadence SoC Encounter

Design Flow

l 

Input Files:

l  Generated and verified files from logic synthesis

l  Gate Level Netlist (.v file)

l  SDC file: Standard Delay Constraints, Generated by logic synthesis tool l  Technology Files:

l  LEF file:

§  Standard-cell layout information, Contains layer, via and macro definition

l  Lib file (.TLF)

§  Standard-cell timing information, e.g. delay and capacitance

l 

Output Files:

l  GDSII: database file format which is the industry standard for data exchange

of IC layout design information.

l  DEF file: Design exchange format to output the design so it is readable by

Design Import

Toplevel of the design Veriglog Netlist File

.Lib .TLF Files .LEF File .SDC File

Design Import

Flattening the Netlist: Logic

Hierarchy and Physical Hierarchy

Top A A1 B A3 A2 A4 C RAM C1 C2 C3 Netlist - hierarchical

= leaf cell (std or macro cell)

Layout view – FLAT!

A1 A3 A2 A4 RAM C1 C2 C3 Top

The Layout is Flat – The netlist is not

Top

A1 A2 A3 A4 C1 C2 C3 RAM

Floor Planning

l 

The floorplanning problem is to plan the positions and

shapes of the modules at the beginning of the design

cycle to optimize the circuit performance:

l  chip area

l  total wirelength

l  delay of critical path

l  Routability

PS Step 2: Floorplan

RAM

Setting X/Y_BOUNDS Of CLUSTER or CELL

Setting XY location of CELL

Creation of core area for rough placement

Creation of SITEs for detailed placement

Automatic Floor Planning

Automatic Floor Planning:

l  Analyzes the data flow between design blocks based on their

connectivity and their location

l 

Relative Floor Planning:

l  Capture and define the placement relationship of floorplan

objects independently from the actual coordinates in a floorplan

l  flexible way to place objects, such as modules, blocks,

groups, blockages, pin guides, pre-routed wires, and power domains

l  I/O pins can be used as reference objects but they cannot be

Pre-route example:

S1 and S2 are relative to the object I2 and the

Core_Boundary

Floorplanning example

Floor Planning

l 

Aspect Ratio

l  Height/Width l 

Core Utilization

l  Area of Stand. Cell/Area of Core

l 

Core to IO Boundary

l  Distance from IO Boundary

l 

Core to Die Boundary

Partitioning

l 

Part of Floor Planning

l 

Standard Cells are in Floating States before placement.

l  Have not been assigned a fixed location in Core

l  Time to define clusters and regions

l  To keep time critical component close

l 

Soft Regions

l  Boundary can change during standard cell placement

l 

Hard Regions

Power Planning

l 

Deal with Power Distribution Network

l 

Power nets are considered as special nets.

l  Need to consider current density (IR drop).

l 

Three levels of Power Distribution

l 

Rings

l  Carries VDD and VSS around the chip

l 

Stripes

l  Carries VDD and VSS from Rings across the chip

l 

Rails

Power Planning

VDD VSS

Rings Stripes (vertical or horizontal)

Rails

Power Distribution network

Example

Placement

l 

Global placement (rough location)

l 

Detailed placement (legalization)

l 

Two associated cost functions

l 

Reduce total wiring or routing length

l 

Distribute standard cell instances homogeneously in

ASIC Core such that optimal equilibrium among

vertical and horizontal routing is achieved

Placement Problem Formulation

Input:

l  Blocks (standard cells and macros) B₁, ... , B_n

l  Shapes and Pin Positions for each block B_i

l  Nets N₁, ... , N_m l 

Output:

l  Coordinates (x_i , y_i ) for block B_i.

l  No overlaps between blocks

l  The total wire length is minimized

l  The area of the resulting block is minimized or given a fixed

die

bad placement good placement

Detailed Placement

l 

After global placement

l 

To Refine placement based on congestion, timing and

power

l 

Congestion Driven Placement

l 

To distance standard cell instances from each other such

that more routing tracks are created between them

Timing Driven Placement

l 

To optimize large sets of path delays

l 

Net Based

l 

Try to control the delay on signal path by imposing an

Floor planned

Hard Block

Placement

Unconstrained

Placement

Clock Tree Synthesis

Automatic insertion of buffers along the clock path to balance the clock delay to all Flip Flops. Main concerns for clock design?

l  Skew

l  For increased clock frequency, skew may contribute over 10% of the

system cycle time

l  Delay

l  Minimize the propagation delay

l  Area

l  Number of buffers and total wire length

l  Power

l  It switches at every clock cycle, a major power consumer!

l  Slew rate is important (sharp transition)

l  Noise

May need shielding, Clock is often a very strong aggressor

Columbia University

Clock Tree: General Concepts

Skew Power

Area Slew rates

Unbuffered clock tree Buffered/balanced clock tree

Advanced clock tree synthesis

methods

l 

0-skew clock tree synthesis

l 

Clock tree synthesis considering process

Clock Distribution

Clock tree generation based on

structure and load balance (H-tree)

Clock tree generation based on

structure and load balance (H-tree)

Structure balance Structure and load

balance

Clock tree generation based on

structure and load balance (Fish-bone)

Clock tree generation based on

structure and load balance (Fish-bone)

Taping point

H-Tree: Structure Balancing

CTS considering process variations

l  P-variations cause unpredictable delay variations in transistors and

wires -> uncontrollable skew

l  The delay variations in common part of clock tree between launch

and capture flops do not cause skew

l  Goal is to minimize non-common

part of clock tree between Launch and capture clock nodes

D

Q D Q

Combinational Logic

clk

Without On-Chip Variation Awareness

D

Q D Q

Combinational Logic

Clock Tree Synthesis in SoC

Encounter

Clock Tree Synthesis in SoC

Encounter

Routing Fundamentals

•  Goal is to realize the metal/copper connections between the pins

of standard cells and macros ▫  Input :

–  placed design

–  fixed number of metal/copper layers ▫  Goal:

–  routed design that is DRC clean and meets setup/hold timing

•  Consists of two phases

1. Global route: To estimate the routing congestion 2. Detail route: To assign the nets to the routing tracks

Standard cell pin

Interconnect Organization

l 

In 65 nm technology, up to 12 metal layers for

routing

l 

Higher metal layers: Wider, less resistance

Proper for assigning global wires and clock nets

l  Less delay, less power consumption

l 

Power nets are always assigned to the top level metal

layer

Routing Issues for 90nm Technology

and Beyond

1. 

Timing driven routing

2. 

Signal integrity aware

3. 

DRC

1- Timing-Driven Routing

l 

At 90nm net delay becomes significant

l  Quality of route can effect timing l 

Optimize critical paths

l 

Route some nets first (Net weights)

l  Order of routing (priorities : eg. Default : Clocks 50, others 2)

l  Most routing freedom at start

l  Use shortest paths possible

l 

If you have a congested design you may need to set the

2- What is Signal Integrity or SI?

Aggressor Victim

net 1

net 2

Signal delay caused by crosstalk noise

What is SI?

Extra clock cycle!

à Functional Failure

^

Crosstalk Prevention : Routing

Routing solution

Limit length of parallel nets

Wire spreading (skip track - clocks) Shield special nets

3- DRC (Design Rule Check)

• 

Design rules: Guidelines about the geometry

constraints for constructing process masks

• 

Information like:

•  Routing layers: width, spacing , pitches

• 

General Rules:

•  a) enclosure, b) space, c) overlap

d) width, e) extension

• 

Specific rules

•  Antenna rules, metal density rules, minimum area

• 

A compromise between performance and yield

▫  More conservative rules increase probability of correct

circuit function (yield)

a

b c

d

45

DRC Challenges

800 Count of Design rules in the runset

The number of design rules in the DRC runsets for different technology processes

Reasons:

-  More metal layers

-  Diff spacing rules depending on width

-  Recommended rules è general rules

4- Optical Proximity Correction

(OPC)

Mask Layout Data ->Physical Mask

Mask layout data

physical mask?

mask layout data

fracture

mask writer

physical masks

(ALTA 4700 mask writer)

Resolution Enhancement Techniques

6

Basic lithographic system

[source: Schellenberg/IEEE Spectrum] Basic Lithography

RC Extraction

l 

RC extraction is the calculation of all the

routed net capacitances and resistances

l 

Used for

l 

Delay calculation

l 

Static Timing Analysis

l 

Circuit Simulation

Electromigration

•  Electromigration is the movement of the lattice ions of the

interconnect material as the result of the momentum transfer form electrons.

•  High current density or irregular shapes for the interconnects

Power Analysis

l 

Power analysis

l 

Reduces risk of IR voltage drops in power nets

l 

Reduces Electromigration effects due to high current

density

l 

Resistance of power and ground net extracted

l 

Average current of each transistor connected to

power net is calculated

l 

Average currents are distributed throughout the

power net

Power Analysis

l 

Average power is sufficient when "time constants" of

effects are large

l  Battery Life

l  Thermal Analysis

l 

VCD is needed to simulate instantaneous power (current)

l  Necessary for estimation of Simultaneous Switching Noise (SSN)

Energy Calculation

l 

Save your design as a Verilog Netlist

l 

Simulate the Design in NCSim/ModelSim

l 

Create a VCD File

l 

Restore the Design in Encounter

l 

Read the VCD Activity file

l 

Report Power to get the average power

VCD File Script

run -timepoint 0 ns -absolute

database open /media/disk1/mdpu/ADD2/MAC_0.vcd

-vcd -default -timescale us

probe -create :mTile -vcd -all -depth all

run -timepoint 100 us -absolute

Power Calculation in

Encounter

restoreDesign /home/ali/PhysicalDesign/ICAD2/mdpu/ Tile_final.enc.dat Tile

extractRC -outfile file.cap

read_activity_file -format VCD -vcd_scope Tile_tb/mTile /media/ disk-1/mdpu/ADD2/MAC_0.vcd

reportPower -noRailAnalysis -outfile /media/disk-1/mdpu/ADD2/ reports/powenc_0.rep

Verification

l 

The complete placed and routed design is verified

before fabrication

l 

Functional Verification

l 

Verification is performed against behavioral RTL pre-layout

and post-layout structural description (netlist) for the design

validation.

l 

Rule Based

l 

Assertion based verification

l  Assertions macros are expressions that, if false, indicate

and error

LVS(Layout vs. Schematic)

LVS

vdd

IN OUT

vss

Extract the designed devices (nmos, pmos,n-well tap,…) Extract the connectivity between

Top level labels needed for VDD,VSS, inputs and outputs