IET Power Electronics
Research Article
Analysis of an efficient interleaved ultra-large
gain DC–DC converter for DC microgrid
applications
ISSN 1755-4535 Received on 1st October 2019 Revised 13th March 2020 Accepted on 25th March 2020 E-First on 29th April 2020 doi: 10.1049/iet-pel.2019.1138 www.ietdl.orgNaser Vosoughi Kurdkandi
1, Tohid Nouri
21Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran 2Department of Electrical Engineering, Sari Branch, Islamic Azad University, Sari, Iran
E-mail: [email protected]
Abstract: This study deals with steady-state analysis and control of a step-up interleaved winding cross-coupled inductor DC– DC converter with high voltage gain and reduced voltage stress across semiconductors using voltage multiplier cells (VMCs). Because of the interleaved scheme, the thermal stress is reduced and the input current ripple is minimised. The leakage energy is recycled by passive lossless clamp circuit to the output. Meanwhile, the voltage stress across the semiconductors is substantially low. Hence, MOSFETs with less ON-state resistances and diodes with a less forward voltage drop can be utilised that improves the circuit performance. The operation principle and the steady state are discussed. Small-signal modelling of the proposed converter is derived via state-space averaging technique and a dual loop controller for output voltage regulation is designed. The adopted strategy utilises a fast dynamical inner loop to control the input current and an outer loop for the output voltage regulation. Finally, a 1 kW prototype with 60 V–1 kV voltage conversion is fabricated and tested to probe the carried analysis.
1 Introduction
A DC microgrid is a controllable network having its own distributed generation sources, loads and energy storage units. In comparison with AC microgrid, the DC microgrids have the advantages of reduced power conversion stages, decoupling from the supply frequency, and better integration of energy storage and distributed (renewable) energy sources such as photovoltaic (PV) and fuel cell (FC) with increased overall system efficiency at reduced costs and sizes [1]. Low voltage DC microgrids (e.g. 1 kV bus) that consist of both regular service loads and sensitive equipment are interesting for application in data centres, building, and grid-connected renewable energy systems. Therefore, the integration of low voltage renewable energy sources such as PV and FC (up to 50–60 V) to a DC microgrid system demands for ultra-large gain and high-efficiency DC–DC converter [2].
The simplest solution is the conventional boost converter. However, to achieve high voltage gains, the converter should be operated around unity duty cycle, which seriously degrades the conversion efficiency and limits control criteria. Also, more expensive semiconductors should be selected to tolerate high voltage stress. Some topologies based on the switched capacitor and coupled inductors have been proposed to overcome the disadvantages of the conventional boost converter [2–12]. These solutions realise high voltage gain at moderate duty cycles and the voltage stress across the semiconductors in decreased successfully. Despite the advantages of the mentioned solutions, the efficiency of the single switch converters degrades at high power levels and the semiconductors suffer from high current/thermal stress. Interleaved structures can overcome this phenomenon by the distribution of the input current between the phases and consequently decrease the conduction losses and increases the conversion efficiency at high current and high power applications [13–26]. Also, the input current ripple is minimised that maintains the life time of the renewable power sources. An efficient modular high voltage gain interleaved boost converter is proposed in [13] that integrates a forward energy-delivering circuit with a voltage-doubler for DC microgrid applications. More modules can be paralleled to increase the power level and the dynamic performance for higher powers. Built-in transformer voltage multiplier cell (VMC) technique is utilised in [14–16] to achieve high voltage
gain with high power density. The direct energy transfer concept is employed to propose a family of non-isolated step-up interleaved converters making the turns ratio of a built-in transformer as another design parameter for obtaining higher gains. To improve current sharing performance, high step-up converters with winding cross-coupled inductors (WCCIs) have been presented in [17, 20]. High voltage gain, low voltage stress across power MOSFETs and reduced peak current ripple are the advantages of these converters. The converters in [21, 22] employ coupled inductor VMCs to achieve high voltage gain at moderate duty cycles. The interleaved boost converter and a voltage-double module are connected in series in the converter of [23]. The secondary sides of the coupled inductors are in interleaved series connection and shared by two voltage-double modules to handle the interleaved energy storage. An interleaved high step-up converter with a coupled inductor and built-in transformer is presented in [24] which gives a more flexible design by adding an extra degree of freedom for voltage gain extension.
This paper proposes an ultra-large gain DC–DC converter with the following features:
(i) Ultra-large voltage gain and minimised voltage stress. (ii) Low input current.
(iii) The leakage energy is successfully recycled to the output by the passive clamp circuit, which avoids the large voltage spikes across MOSFETs and improves the conversion efficiency.
(iv) The diodes are switched at zero current switching (ZCS) and the reverse current recovery problem is alleviated due to the leakage inductances.
(v) Minimised input current ripple.
This paper is organised as follows: in Section 2, the principle operation is discussed; in Section 3, the steady-state analyses are given, in Section 4, the design guidelines are listed; in Section 5, the control process is described; in Section 6, the performance comparison is given; Sections 7 and 8 deal with experimental verification and conclusion, respectively.
2 Proposed converter and principle of operation
The circuit schematic of the proposed converter is shown in Fig. 1. LK1 and LK2 are the leakage inductances; Lm1 and Lm2 are the
magnetising inductances; Cr11, Cr12, Cr21, and Cr22 are the
regenerative capacitors; Co1, Co2, and Co3 represent the output
capacitors; S1 and S2 are the power MOSFETs; CS1 and CS2 are
parasitic capacitors of MOSFETs; DC1 and DC2 are the clamp
diodes. The turns ratio of coupled inductor N is equal to N2/N1.
There are two sets of three windings coupled inductors in the proposed converter. The primary windings of the coupled inductors have the same performance as the inductors in the conventional interleaved boost converter. The secondary winding couples with its primary winding in its phase and the tertiary winding couples to its primary and secondary windings in another phase. The second and third windings of the coupled inductors serve as DC voltage source and are inserted in series to the circuit with a stacked scheme that helps to reduce the voltage stress across the MOSFETs. The following assumptions are made to simplify the analyses:
(i) The voltage of all capacitors is considered constant in one switching period.
(ii) The components are ideal, except that the body capacitors of the MOSFETs are considered.
Generally, the interleaved converters are favourable to work at duty cycles higher than 0.5. This is mainly due to this fact that at D < 0.5, the voltage gain is low and also input current ripple gets large, which can affect the input power sources such as PV and FC. Therefore the performance operation is performed for D > 0.5. The key waveforms and the equivalent circuits of the proposed converter are shown in Figs. 2 and 3, respectively. Due to the completely symmetrical interleaved structure, the operating modes I to V and VI to X are mutually symmetrical. Therefore, only the operating modes I to V are described.
Mode I [t0< t < t1]: The equivalent circuit is shown in Fig. 3a.
At t = t0, S1 is turned-on. CS1 is discharged, rapidly. Due to leakage
inductances, the currents through the windings of coupled inductors are decreased linearly and the reverse recovery problem of the diodes is alleviated. iLK1 is increased rapidly and when it
reaches to iLm1 at t = t1, this mode is ended.
Mode II [t1< t < t2]: Due to maximum subfigure limitation of
the journal format the equivalent circuit at this mode is not presented. At t = t1, the current that flows through the LK1, gets
equal to iLm1. The current through the secondary and tertiary
windings of coupled inductors are zero at this mode. MOSFETs S1
and S2 are in on state and other semiconductors are in a
turn-off state. Output capacitors provide energy for the load. The leakage and magnetising inductances are charged, linearly:
iLk j(t) = iLmj(t) = iDS j(t) = ILmj(t0)
+Llk jV+ Lin
mj(t − t0), j = 1, 2
(1)
Mode III [t2< t < t3]: The equivalent circuit is shown in Fig. 3b.
At t = t2, S2 is turned off. The parasitic capacitor CS2 is rapidly
charged by the current iCS2(t) = iLm2(t). Consequently, the drain–
source voltage of S2 (VDS2) increases until it reaches to the VCo1
plus threshold voltage of DC2. The clamp diode DC2 begins to
conduct at t = t3 and this mode is ended
VDS2(t) =ILmCS2(t2)
2 (t − t2) (2)
Mode IV [t3< t < t4]: The equivalent circuit is shown in Fig. 3c.
DC2 is on and the voltage across the S2 is clamped at VCo1. The
leakage energy is recycled to the output. This mode ends at t = t4 when the leakage energy is fully released
iS1(t) = iLk1(t) = iLm1(t3) + N 2iDr11(t) + iDo2(t) (3)
iDC2(t) = iLk2(t) = iLm2(t3) − N 2iDr11(t) + iDo2(t) (4)
Mode V [t4< t < t5]: The equivalent circuit is shown in Fig. 3d. At
this mode DC2 is off and the energy of the Lm2 is transferred to Cr11,
Cr21 and load Ro. This mode ends at t = t5 when S2 is turned-on and
the next half switching cycle begins.
iLm2(t3) = N 2iDr11(t) + iDo2(t) (5)
3 Steady-state
analysis
of
the
proposed
converter
Since the time duration of modes I, III, VI, VIII are significantly short, they are not considered in the analysis. Due to the symmetry of the proposed converter, we have
Fig. 1 Circuit configuration of the proposed converter
Fig. 2 Key waveforms of the proposed converter
ILm1= ILm2= ILm (6) VCr11= VCr12= VCr21= VCr22= VCr (7) where ILm1 and ILm2 are the average currents that flow through the
magnetising inductances. The average value of current through the clamp diodes is equal to Io/2 and the average current that flows
through the other diodes is equal to Io. By equating the surfaces of
red and purple closed lines in Fig. 2 (see iLk1) to 3NIoTS and IoTS/2,
respectively, we have
DC= 2(1 − D)6N + 1 (8)
ILm= 6N + 12(1 − D)Io (9)
The voltage stress across S2 during modes IV and V can be written
as below:
VDSIV2= VCo1 (10)
VDSV1= VNCr (11)
According to Fig. 2 and using (8) and (9), the voltage across the leakage inductors can be expressed as
VLkIV1= − VLkIV2= Lkdidt = LLk kDILm
CTS=
LkfS(6N + 1)2Io
4(1 − D)2 (12)
Referring to the equivalent circuit of Fig. 3c, the following equations can be obtained in mode IV:
VCr= N(2VLkIV2+ VCo1) (13)
VCo3= 2VCr+ NVCo1+ 2NVLkIV2= 3VCr (14) The output voltage can be expressed as below:
Vo= VCo1+ 2VCo3 (15)
Using (12)–(14), the following equations can be derived: VCo1= VDS,max= VDC,max= 6N + 1 +Vo 3N(6N + 1)LR kfSVo
o(1 − D)2 (16)
VCr=VDr2, max= VDo2, max =6N + 1 −NVo N(6N + 1)Lk2(1 − D)2RfSVo
o (17)
The average voltage across S2 is given by the following equation:
DCVDSIV2+ (1 − D − DC)VDSV2= Vin (18)
substituting (10), (11), (13) and (15) into (18), the voltage gain at continuous conduction mode (CCM) is obtained as
MCCM= 1 + 6N
(1 − D) 1 + 1 + 6N1 − D 2LkfS
2Ro
(19) Considering ideal coupled inductors with zero value of the leakage inductance, the voltage gain is obtained as
VCo1= VDS, max= VDC, max=1 − D =Vin 6N + 1Vo (20)
VCr= VDr2, max=VDo2, max= VCo3 = NV3 Co1= 6N + 1NVo (21)
MCCM= VVo
in = 6N + 1(1 − D) (22)
4 Design guidelines of the proposed converter
4.1 Design of coupled inductors
Lm is designed to ensure the proposed converter operates in CCM. Lm can be obtained by
Lm>D(1 − D)(6N + 1)22Rfo
S (23)
After specifying the duty cycle and the input voltage, the turns ratio of the coupled inductor should satisfy the following equation:
N = (1 −D)M6CCM− 1 (24)
After designing the required value of Lm for CCM operation, the value of N1 can be obtained by
N1= LBmILm,Max
MaxAC (25)
where ILm,Max is the maximum value of the current through
magnetising inductance, BMax is the maximum of the magnetic flux
density and AC is the core cross-sectional area of the coupled inductors. Using (24), the value of N2= N3 is yield.
Fig. 3 Equivalent circuits of the proposed converter at CCM operation in
half switching cycle
(a) Mode I, (b) Mode II, (c) Mode IV, (d) Mode V (Mode III is omitted due to
maximum subfigure limitation of the journal format)
4.2 Selection of semiconductors
The voltage stress across the MOSFETs and power diodes can be obtained from (20) and (21). Also, the RMS current of the semiconductors are as below:
IS,RMS= 2(1 − D) (6N + 1)Io 2(2D − 1) + (12N + 1)2(1 − D) (26)
IDr,RMS= IDo,RMS= 1 − DIo (27)
IDC,RMS= Io 2(1 − D)6N + 1 (28)
4.3 Selection of capacitors
The capacitors are designed in such a way that their corresponding voltage ripple is limited to a specific value. By applying this principle, the value of the capacitors can be formulated as:
Cr= Po VoΔVCrfS (29) Co1=2V Po oΔVCo1fS (30) Co2= Co3= V Po oΔVCo2fS (31)
where ΔVCr, ΔVCo1 and ΔVCo2 are the voltage ripple across Cr, Co1
and Co2, respectively.
5 Small-signal modelling and controller design
The state-space averaged model of the proposed converter is obtained under the following considerations: (1) power MOSFETs and diodes are ideal; (2) equivalent series resistances (ESRs) of coupled inductors and output capacitors of the proposed converter are neglected; (3) only one of the regenerative capacitors in each VMC is considered as state variable (Cr11, Cr12→ Cr1 and
Cr21, Cr22→ Cr2); (4) the ESR of the regenerative capacitors is
considered rC; (5) converter operates under CCM, and is in steady-state; (6) the leakage inductances are neglected; (7) charging and discharging intervals of the drain–source capacitance of the power switches are neglected; and (8) the input voltage is constant. Four intervals can be considered during one switching period. The small-signal model can be derived as follows.
5.1 State-space modelling
Intervals I and III: When both of the power switches S1 and S2 are
in ON-state; the state equations can be written as below according to the equivalent circuit of Fig. 3b
diLm1 dt =LmVin1 diLm2 dt =LmVin2 dvCr1 dt = 0 dvCr2 dt = 0 dvCo1 dt = −RvCooCo11− vCo2 RoCo1− vCo3 RoCo1 dvCo2 dt = −RvCooCo12− vCo2 RoCo2− vCo3 RoCo2 dvCo3 dt = −RvCooCo13− vCo2 RoCo3− vCo3 RoCo3 (32)
Interval II: When S1 is in ON-state and S2 is in OFF-state; the state
equations can be written as below according to the equivalent circuit of Fig. 3c diLm1 dt =LmVin1 diLm2 dt =−vLmCo21+ Vin Lm2 dvCr1 dt =−vrCCrCr11+ NvCo1 rCCr1 dvCr2 dt =−vrCCrCr22− NvCo1 2rCCr2+ vCo3 2rCCr2 dvCo1 dt =iLmCo12+ 2 NvCr1 rCCo1 − NvCr2 rCCo1− 5N 2 2rC + 1Ro vCo1 Co1 − vCo2 Co1Ro+ N2rC− 1Ro vCo3 Co1 dvCo2 dt = −RvCooCo12− vCo2 RoCo2− vCo3 RoCo2 dvCo3 dt =rvCrCCo23+ N2rC− 1Ro vCo1 Co3 − vCo2 RoCo3− 12rC+ 1Ro vCo3 Co3 (33)
Interval IV: When S1 is in OFF-state and S2 is in ON-state; state
equations can be obtained by (due to symmetry of the operations, the equivalent circuit of this mode has not been shown in Fig. 3)
diLm1 dt =−vLmCo11+ Vin Lm1 diLm2 dt =LmVin2 dvCr1 dt =−vrCCrCr11− NvCo1 2rCCr1+ vCo3 2rCCr1 dvCr2 dt =−vrCCrCr22+ NvCo1 rCCr2 dvCo2 dt =rvCrCCo12+ N2rC− 1Ro vCo1 Co2− 12rC+ 1Ro vCo2 Co2 − vCo3 RoCo2 dvCo3 dt = −RvCooCo13− vCo2 RoCo3− vCo3 RoCo3 (34)
5.2 State-space averaged model
It is clear that the weighting factors for each of the four operation modes are (d − 1/2), (1 − d), (d − 1/2), and (1 − d) in sequence, respectively [14]. Hence, the state-space averaging technique can be served to combine the state equations of four modes into the state-space averaged equation in matrix form as
x˙= Ax + Bu, y = Cx (35)
where x= [iLm1iLm2vCr1vCr2vCo1vCo2vCo3], u = [Vin], y = [vo].
A (see (36)), B, and C are obtained by (see (36))
B= 1/Lm1 1/Lm2 0 0 0 0 0T (37)
C= 0 0 0 0 1 1 1 (38)
5.3 Introduction of perturbations and obtaining of a small-signal linearised model
The perturbation is applied to the state variables and other quantities around the steady-state point in (35) as (see (39)) . By comparing the DC and AC quantities while neglecting the second-order terms, the small-signal model of the proposed converter can be obtained as
x~˙= A′x~+ Dd~, y~= Cx~ (40)
where A′ (see (41)) and D are below: (see (41))
(see (42))
5.4 Controller design
In this step, a closed-loop controller is developed for the proposed converter. The component specification is the given values in Table 1 for laboratory validation. The open-loop poles and zeros for the transfer functions of the duty cycle to input current
i~in(s)/d~(s) and duty cycle to output voltage v~o(s)/d~(s) is shown in
Fig. 4. The system is naturally stable due to left-half-plane poles. Right-half-plane zero can be observed in v~o(s)/d~(s). Hence,
conventional voltage mode control cannot realise sufficient dynamic performance due to narrow closed-loop bandwidth. By employing the current control mode, the zeros are placed in the left-half-plane and the dynamic performance will be significantly improved. Therefore, a dual-loop control system is designed for the proposed converter, which its block diagram is shown in Fig. 5.
A= 0 0 −(1 − d)Lm 1 0 0 0 0 0 0 −(1 − d)Lm 2 0 0 0 0 0 0 −2(1 − d)rCCr 1 0 N(1 − d) 2rCCr1 1 − d 2rCCr1 0 0 0 0 −2(1 − d)rCCr 2 N(1 − d) 2rCCr2 0 1 − d 2rCCr2 1 − d Co1 1 − d Co1 N(1 − d) rCCo1 N(1 − d) rCCo1 − 5N 2(1 − d) rCCo1 − 1RoCo1 N(1 − d) 2rCCo1 − 1RoCo1 N(1 − d) 2rCCo1 − 1RoCo1 0 0 1 − drCCo 2 0 N(1 − d) 2rCCo2 − 1RoCo2 − 1RoCo2 − 1 − d2rCCo2− 1RoCo2 0 0 0 1 − drCCo 3 N(1 − d) 2rCCo3 − 1RoCo3 − 1 − d2rCCo2− 1RoCo2 − 1RoCo2 (36) d = D + d~, iLm1= ILm1+ i~Lm1, iLm2= ILm2+ i~Lm2 vCr1= VCr1+ v~Cr1, vCr2= VCr2+ v~Cr2 vCo1= VCo1+ v~Co1, vCo2= VCo2+ v~Co2, vCo3= VCo3+ v~Co3, vo= Vo+ v~o (39) A′ = 0 0 −(1 − D)Lm 1 0 0 0 0 0 0 −(1 − D)Lm 2 0 0 0 0 0 0 −2(1 − D)r CCr1 0 N(1 − D) 2rCCr1 1 − D 2rCCr1 0 0 0 0 −2(1 − D)r CCr2 N(1 − D) 2rCCr2 0 1 − D 2rCCr2 1 − D Co1 1 − D Co1 N(1 − D) rCCo1 N(1 − D) rCCo1 − 5N 2(1 − D) rCCo1 − 1RoCo1 N(1 − D) 2rCCo1 − 1RoCo1 N(1 − D) 2rCCo1 − 1RoCo1 0 0 1 − Dr CCo2 0 N(1 − D) 2rCCo2 − 1RoCo2 − 1RoCo2 − 1 − D2rCCo2− 1RoCo2 0 0 0 1 − Dr CCo3 N(1 − D) 2rCCo3 − 1RoCo3 − 1 − D2rCCo2− 1RoCo2 − 1RoCo2 (41) D= VCo1 Lm1 VCo1 Lm2 2VCr1 rCCr1− NVCo1 2rCCr1− NVCo2 2rCCr1 2VCr2 rCCr2− NVCo1 2rCCr2− NVCo3 2rCCr2 −ILm1 Co1 − ILm2 Co1 − NVCr1 rCCo1 − NVCr2 rCCo1 + 5 N2VCo 1 rCCo1 − NVCo2 2rCCo1− NVCo3 2rCCo1 − VCr1 rCCo2− NVCo1 2rCCo2+ VCo2 2rCCo2 − VCr2 rCCo3− NVCo1 2rCCo3+ VCo3 2rCCo3 (42)
The outer loop provides the reference current for the inner loop. In the inner current control loop, TCi(s) is the transfer function of the PI controller, TM is the transfer function of the modulator, Tid(s)
is the transfer function of the duty cycle to input current and the Hi(s) is the transfer function of the current sensor. In the outer voltage control loop, TCv(s) is the transfer function of the PI Table 1 Performance comparison of the proposed converter
Topology Converter in [19] Converter in [24] Proposed converter
active switches 2 2 2
diodes 6 6 8
number of magnetic cores 2 2 2
number of windings 6 7 6
number of capacitors 5 5 7
voltage gain (MCCM) 2(N + 1)
1 − D 2(n + 1) + N1 − D 6N + 11 − D voltage stress of power MOSFETs (VDS) Vo
2(N + 1) 2(n + 1) + NVo 6N + 1Vo maximum voltage stress across diodes (VD,Max) (2N + 1)Vo
2(N + 1) (2N + 1 + n)V2(n + 1) + Nout 6N + 12NVo
Fig. 4 Open-loop poles and zeros (a) v~o(s)/d~(s), (b) i~in(s)/d~(s)
Fig. 5 Developed dual loop controller
controller, Tvi(s) is the transfer function of the input current to the output voltage, and the Hv(s) is the transfer function of the voltage sensor.
5.4.1 Current loop control design: Fig. 6a shows the block diagram of the inner current control loop. Input current is feedback to the controller with the gain of Hi(s). The output of the PI controller is compared with a sawtooth wave in the modulator to generate the gate pulses of the power MOSFETs.
The PI controller parameters should be designed properly to realise the minimisation of steady-state error and relatively fast dynamic performance. From the state-space analysis, the transfer function of the i~in(s)/d~(s) is obtained as follows: (see (43)) . The
gain of the modulator is selected as below:
TM(s) = 113.2 (44)
By assuming the maximum input current as 25 A and the maximum limit of the output voltage controller at 2.5 V, the transfer function of the current feedback sensor is obtained as
Hi(s) = 110 (45)
The open-loop transfer function of the current control loop is Tol,i(s) = Tci(s) × TM(s) × Tid(s) × Hi(s) (46)
The parameters of the PI controller are designed to have a PM of 60° at the crossover frequency of 3.3 kHz, which gives
Kp= 2.6643 and Ki= 3.1897 × 104 [25, 26]. The value of the time
constant of the controller is 83.53 μs. The frequency response of the uncompensated and compensated systems for current control loop is shown in Fig. 6b. It can be seen that the designed values for the PI controller realises the PM of 61° at the crossover frequency of 3.4 kHz and also the low-frequency gain is improved compared to that of uncompensated value.
5.4.2 Voltage loop control design: Fig. 6c shows the block diagram of the inner current control loop. The outer voltage control loop regulates the output voltage by providing the reference input current for the inner control loop. The cross over frequencies of the outer and inner control loops are sufficiently far apart from each other. Then the dynamic of the current control loop is neglected while designing the voltage control loop. The transfer function of the input current to the output voltage v~o(s)/i~in(s) is given in (47).
The voltage reference in the processor is set as 2.7 V. Then, the transfer function of the voltage sensor is selected as
(see (47))
Hv(s) = 1388 (48)
The open-loop transfer function of the voltage control loop is Tol,v(s) = Tcv(s) × Tvi(s) × Hv(s) (49) The parameters of the PI controller are designed to have a PM of 60° at the chosen crossover frequency of 40 Hz, which gives Kp= 151.2969 and Ki= 2.5648 × 104. The value of the time
constant of the controller is 5.9 ms. The frequency response of the
Fig. 6 Control block diagrams and frequency responses of the proposed converter
(a) Inner loop controller, (b) Frequency response of the compensated and uncompensated system for an inner current loop, (c) Outer loop controller, (d) Frequency response of the
compensated and uncompensated system for outer voltage loop
Tid(s) =i ~ in(s) d~(s) = 9.375 × 10s7+ 2.248 × 105s66s+ 2.107 × 106+ 1.615 × 1012s125s+ 1.514 × 105+ 3.705 × 1018s174s+ 3.473 × 104+ 7.437 × 1023s213s+ 6.973 × 103+ 2.503 × 1027s232+ 1.735 × 10s2+ 1.701 × 1029s − 8.591 × 1027s − 1.112 × 101817 (43) Tvi(s) = v ~ o(s) i~in(s) = −4.9 × 109.375 × 1054ss66+ 2.107 × 10− 9.889 × 101210ss55+ 1.514 × 10− 6.102 × 101816ss44+ 3.473 × 10− 1.058 × 102322ss33+ 6.973 × 10− 3.457 × 102724ss22+ 1.735 × 10+ 4.46 × 103029s − 1.623 × 10s − 8.591 × 101918 (47)
uncompensated and compensated systems for current control loop is shown in Fig. 6d. It can be seen that the designed values for the PI controller realises the PM of 62° at the crossover frequency of 43 Hz and also the low-frequency gain is improved compared to that of uncompensated value.
6 Performance comparison
In order to clearly demonstrate the advantages of the proposed converter, a comparison has been made between the proposed converter and converters published in [19, 24] in Table 1. The presented competitors in the references are favourable for DC microgrids and other applications such as high step-up high power conversion. Unfortunately, the proposed converter has two more diodes and capacitors. Fig. 7 shows the comparison of the voltage gain and voltage stress across the switching devices. The proposed converter has the highest voltage conversion ratio and the lowest voltage stress across MOSFETs and diodes. Then semiconductors with low ON-state resistances and low forward voltage drops can be adopted and the conversion efficiency can be maintained at a
reasonable level. Accordingly, having two more diodes and capacitor can be covered by the advantages of the proposed converter. Hence, the proposed converter is a suitable candidate for the integration of renewable sources to DC microgrids.
7 Simulation and experimental verification
Simulation results of the proposed converter in PSCAD-EMTDC along with the experimental results of a fabricated prototype circuit (Fig. 8) are presented to demonstrate the performance operation and the specifications of the converter are shown in Table 2. Figs. 9 and 10 show the simulation and experimental steady-state measured voltage and current of the proposed converter under full load, respectively. To fully probe the carried steady-state analysis, these measurements have been done with a nominal duty cycle of 60%.
According to (14), (16), (17) and (19), with this value of duty
cycle, Vo= 1005 V, VCr= 133 V, VCo1= 204 V,
VCo2= VCo3= 400 V are obtained.
Fig. 7 Performance comparison (a) Voltage gain, (b) Normalised voltage stress
Fig. 8 Photograph of hardware set-up
Table 2 Circuit specification of the proposed converter
Components Specifications power 1 kW input–output voltage 60–970 V switching frequency 33 kHz regenerative capacitors Cr11= Cr12= Cr21= Cr22= 47 μF output capacitors Co1= Co2= Co3= 220 μF
power MOSFETS/diodes IXTK62N25/MUR1560
coupled inductors EPCOS B66344(Ferrite Core EE55),
N1= N2= N3= 35, turns ratio (N) = 1
Lm= 320 μH, LK= 12 μH, rL1= rL2= 0.1 Ω
Fig. 9a shows the simulation and experimental results of the output capacitors’ voltages, that match to the steady-state analysis.
Figs. 9b and c show the simulation and experimental voltage measurements across the power semiconductors. As can be seen, the voltage stress is substantially lower than the output voltage.
Figs. 10a and b show the simulation and experimental current waveforms of iLk1, iLk2, iDS1 and iDC1. The leakage energy transfers
to the clamp capacitor when the MOSFET turns off and then recovers to the output.
Fig. 10c shows the simulation and experimental current waveforms of iDo1 and iDr11. The reverse-recovery problem is
alleviated dramatically by the leakage inductance; so the
reverse-recovery losses are reduced greatly and the EMI noise is suppressed, significantly.
In order to verify the developed controller scheme, it is implemented in the Beaglebone Black processor by Texas Instrument. The dynamic response of the proposed converter for the load variation between 500 W and 1 kW is shown in Fig. 11. It can be seen that the voltage is well regulated at its reference value.
Table 3 shows the measured efficiency of the proposed converter under different output power. As can be seen, the maximum efficiency is about 96.1% that is occurred at Po= 600 W
and the full load conversion efficiency is about 94.6%.
Fig. 9 Simulation and experimental voltage measurement of the proposed converter under full load Po= 1 kW
(a) Voltages of the Co1, Co2 and Co3, (b) Voltages of MOSFET S1 and diode DC1, (c) Voltages of diodes Do1 and Dr11
8 Conclusion
The steady-state analysis, small-signal modelling and control of a high step-up DC–DC converter have been proposed in this paper. The proposed converter has the advantages of high voltage gain, low voltage stress across power switches and minimised input current ripple. The steady-state analysis has been done carefully. The small-signal modelling of the proposed converter has been presented and it was shown that due to RHP zero in duty ratio to output voltage transfer function, the conventional voltage-mode
control could not realise sufficient dynamic performance. So, a dual-loop controller has been developed for the proposed converter with the concept of current-mode control. The outer loop regulates the output voltage by generating the sufficient reference current for the inner loop, and in this case, the dynamic performance is significantly improved. Finally, in order to show the correctness of the carried analysis, a 1 kW prototype was built and tested.
Fig. 10 Simulation and experimental current measurement of the proposed converter under full load Po= 1 kW
(a) Currents of leakage inductances, (b) Currents of MOSFET S1 and diode DC1, (c) Currents of diodes Do1 and Dr11
Fig. 11 Dynamic response of the proposed converter between 1 kW and 500 W
Table 3 Measured efficiency of the proposed converter
Po, W 200 300 400 500 600 700 800 900 1000
efficiency, % 94.1 94.5 95.2 96 96.1 95.9 95.8 95 94.6
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