Vol. 28, No. 16, (2019), pp. 1786 – 1794
Implementation of Reconfigurable FIR Filter using Logic Optimization Technique
Bala Sindhuri Kandula1, K. Padma Vasavi2, I. SantiPrabha3
[email protected]1, [email protected]2, [email protected]3 University College of Engineering JNTUK, Kakinada1, 3, SVECW, Bhimavaram2
Abstract
The design and implementation of FIR Filter is attaining prominence in digital communications because of its characteristics like BIBO and Stability. Voluminous improvements procured in the VLSI architectures design for FIR Filter for the purpose of reconfiguration. In the real–time implementation of Reconfigurable FIR filters, the accuracy of the acquired signal is achieved by increasing the order of the filter which leads to increase in area .Though the prevailing RFIR Filter designing techniques are effective in various performance metrics, there is still a chance for such a filter design to achieve area efficiency. In this paper, Reconfigurable FIR filter (RFIR) architecture is designed by employing different MAC‟s. Simulation and synthesis are carried out using the Cadence Encounter tool. Comparison of Reconfigurable FIR Filters (RFIR) employing different MAC‟S is performed. From Result analysis, it is observed that RFIR Filter employing Vedic multiplier based on yavadunam sutra and SQRT-CSLA-BEC is area efficient RFIR Filter.
Keywords: RFIR Filter, Vedic multiplier, SQRT-CSLA architecture, Area Efficient Architectures
1. Introduction
In today‟s expanding digital microchip technology in mobile communications, there is a demand for portable, area, power, speed efficient and cost effective DSP architectures.
FIR filtering is achieving notable attention in mobile communications for the removal of noise for its attractive characteristics .While evaluating performance constraints such as area and power in different FIR filtering techniques, a low power RFIR filter architecture is proposed in [1], the filter order is dynamically altered by examining the input signal and filter coefficients. The speed of this architecture is slow as the multiplication and addition are performed by using normal adder and a multiplier. Array multiplier is the very basic fundamental multiplier .But the speed is very less as the combination delay for partial product addition is too high [2]. Different multipliers based on Vedic mathematics have come into existence for the improvement of speed and area. One such multiplier gaining remarkable attention is Vedic multiplier based on yavadunam sutra because of its speed [3]. Similarly one more main module in RFIR filter is an efficient design of adder.
VLSI architecture for SQRT-CSLA adder is definitely one of the optimal choice for speed improvement of an adder as it decides the speed of the RFIR filter In CSLA, due to computation of outputs in advance by assuming the input carry is equal to „zero‟ and
„one‟ and the output can be obtained by using multiplexers [4]-[5].The area for VLSI architerure for SQRT-CSLA adder is achieved by using BEC technique. In this paper, a reconfigurable FIR Filter is designed by employing Vedic multiplier based on yavadunam sutra and SQRT-CSLA adders. Section 2 deals with the VLSI architecture for SQRT- CSLA adders. Section 3 deals with VLSI architecture for Square Architecture based on Yavadunam Sutras .Section 4 deals with Reconfigurable FIR filter employing different multipliers and adders. Section 5 deals with the results and discussion. Section 6 presents the conclusion.
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2. VLSI architecture for SQRT- CSLA Adders
2.1 VLSI Architecture for SQRT-CSLA
Fig.1 16-bit SQRT-CSLA architecture
Table.1. Main Components in 16-bit SQRT CSLA
Group Set Data -Width SQRT-CSLA
Main modules
1 1 2-bit RCA0
2 1 2-bit RCA0
2 2-bit RCA1
2:1 Mux(3)
3 1 3-bit RCA0
2 3-bit RCA1
2:1 Mux(4)
4 1 4-bit RCA0
2 4-bit RCA1
2:1 Mux(5)
5 1 5-bit RCA0
2 5-bit RCA1
2:1 Mux(6)
VLSI architecture for SQRT-CSLA is designed with variable size RCA‟s. The inputs for 16-bit SQRT-CSLA namely “A” and “ B” are divided into different sizes and given as inputs to RCA‟s as shown in Fig.1.The detailed partitions are tabulated in Table-1.The advantage of this architecture is reduction in combinational delay which is achieved by pre-computation of outputs assuming input carry of RCA either „zero‟ and
„one‟[4].
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2.2 VLSI Architecture for SQRT-CSLA
Fig.2. 16-bit SQRT-CSLA-BEC architecture
VLSI architecture for SQRT-CSLA-BEC is designed with variable size RCA‟s and BEC‟s. The inputs for 16-bit SQRT-CSLA namely “A” and “ B” are divided into different sizes and given as inputs to RCA‟s and except for first partition, remaining all RCA‟s outputs are given as inputs to BEC‟s and multiplexers as shown in Fig.2.The detailed partitions are tabulated in Table-2.The advantage of this architecture is reduction in area by reducing gate count with slight increase in combinational delay which is achieved by pre-computation of outputs assuming input carry of RCA either „zero‟ and „one‟.[4]
Table.2. Main Components in 16-bit SQRT-CSLA-BEC
Group Set Data -Width SQRT-CSLA-
BEC Main modules
1 1 2-bit RCA0
2 1 2-bit RCA0
2 2-bit BEC
2:1 Mux(3)
3 1 3-bit RCA0
2 3-bit BEC
2:1 Mux(4)
4 1 4-bit RCA0
2 4-bit BEC
2:1 Mux(5)
5 1 5-bit RCA0
2 5-bit BEC
2:1 Mux(6)
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2.3 VLSI Architecture for SQRT-CSLA-KSA
Fig.3. 16-bit SQRT-CSLA-KSA grouping
Fig.4.Genearlized design of Group-n for SQRT-CSLA-KSA architecture
Table.3 Main Components in 16-bit SQRT-CSLA-KSA
Group Set Data -Width SQRT-CSLA
Main modules
1 1 2-bit KSA0
2 1 2-bit KSA0
2 2-bit KSA1
2:1 Mux(3)
3 1 3-bit KSA0
2 3-bit KSA1
2:1 Mux(4)
4 1 4-bit KSA0
2 4-bit KSA1
2:1 Mux(5)
5 1 5-bit KSA0
2 5-bit KSA1
2:1 Mux(6)
The design for SQRT-CSLA-KSA architecture is carried out by KSA0 and KSA1 .Grouping mechanism for SQRT-CSLA-KSA is as shown in Fig.3. Group1 design
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is carried out by using 2-bit Koggestone adder(KSA).From Group2, generalized form is shown in Fig.4 and tabulated in Table.3[6].
3. VLSI Architecture for Square Architecture based on Yavadunam Sutras (VMY)
Fig.5. Vedic multiplier using Yavadunam Sutra
The steps involved in the design of VLSI architecture for Square architecture based on Yavadunam sutra is discussed in this section [3].
Step 1: A and B are given as inputs to Square Architecture. 2‟s compliment of inputs A and B are taken as deficiencies “D1” and “D2”.
Step 2: Deficiencies D1 and D2 are multiplied by using N-bit Multiplier and from the RHS is obtained.
Step 3: By adding deficiencies D1 and D2 and by using multiplexers and 2‟s compliment the LHS is obtained as shown in Fig.3
The carry obtained by the RHS is added and the sign varies with the input.
If inputs are greater than 2N-1, then LHS = [2N-(D1+D2)] +carry bits from RHS.
If inputs are less than 2N-1, then LHS = (D1+D2)-carry bits from RHS.
If both are mixed, then LHS = [2N-(D1+D2)] +carry bits from RHS.
ADDER 2’S COMP 2’S COMP
N BITS MULTIPLIER 2’S COMP
+/-
OR GATE
OR GATE 1
1
0
RHS PART OF THE PRODUCT LHS PART OF THE PRODUCT
Carry
B
D1 D2
D1 D2
An-1 Bn-1
An-1 Bn-1
A
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4. Reconfigurable FIR Filter
Fig.4. VLSI architecture for Reconfigurable FIR Filter
In this section, RFIR filter architecture is shown in Fig.4.The rudimentary idea is that if the amplitudes of data input and filter coefficients are small, the multiplication executed for x(n) and c(n) is very small; thus, dynamically turning off the multipliers logically has negligible effect on the filter performance. Amplitude Detector logic (AD) is used for the purpose of monitoring the amplitudes of input samples which helps us in turning off multipliers logically. Thus the order of the filter is dynamically altered by turning off multipliers by carefully observing x(n) and coefficients. Instead of using Conventional multiplier, 8-bit Vedic multiplier using yavadunam sutra is used and16-bit addition is carried out by SQRT-CSLA ,SQRT-CSLA-KSA AND SQRT-CSLA-BEC adders.
5. Results and Discussions
RFIR Filter using different MAC units are synthesized using Cadence Encounter Tools.
The different MAC combinations used are
1) Vedic Multiplier VLSI Architecture for Square Architecture based on Yavadunam Sutras (VMY)- Square Root Carry Select Adder(SQRT-CSLA)
2) Vedic Multiplier VLSI Architecture for Square Architecture based on Yavadunam Sutras (VMY)- Square Root Carry Select Adder-KSA(SQRT-CSLA-KSA)
3) Vedic Multiplier VLSI Architecture for Square Architecture based on Yavadunam Sutras (VMY)- Square Root Carry Select Adder-BEC(SQRT-CSLA-BEC)
SQRT-CSLA generally occupies high area when compared to RCA but the combinational delay is very less for SQRT-CSLA. With proper optimization of RCA from the 2nd stage by employing BEC technique, area is optimized but with increase in delay.As gate count is reduced in the architecture ,it shows the reflection in Power also. Thus the total power is also reduced. Koggestone adder is said to be one of the fastest adder. Thus it is used in SQRT-CSLA to check the performance metric „speed‟. Thus, the performance metrics such as Area, delay and ADP for RFIR filter designed with various MAC‟s are
SQRT-CSLA SQRT-CSLA
VMY VMY
z
-1z
-1z
-1VMY
SQRT-CSLA
z
-1z
-1z
-1z
-1z
-1SQRT-CSLA VMY
z
-1AD
Control signal generator
AD
C(0) C(1) C(2) C(n)
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synthesized and tabulated in Table.4.Leakage Power, Dynamic Power and Total Power are tabulated in Table.5.
Fig.5. Area (µm2) for Reconfigurable FIR Filter employing different MAC‟s
Fig.6. Delay (ns) for Reconfigurable FIR Filter employing different MAC‟s
Table 4. Area, Delay and ADP Cadence synthesis results for 4-tap RFIR filter
MAC
Area (µm2)
Delay (ns)
ADP (µm2 *ns) VMY–SQRT-CSLA 14275.134 8953 127805275 VMY–SQRT-KSA 13805.099 8922 123169093 VMY-SQRT-CSLA-BEC 13323.710 9442 125802470
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Fig.7. ADP for Reconfigurable FIR Filter employing different MAC‟s
Fig.8. Leakage Power for Reconfigurable FIR Filter employing different MAC‟s
Area (µm2) for Reconfigurable FIR Filter employing different MAC‟s is shown in Fig.5.
Delay (nSec) for Reconfigurable FIR Filter employing different MAC‟s is shown in Fig.6.
ADP for Reconfigurable FIR Filter employing different MAC‟s is shown in Fig.7 Leakage Power for Reconfigurable FIR Filter employing different MAC‟s is shown in Fig.8. Dynamic Power for Reconfigurable FIR Filter employing different MAC‟s is shown in Fig.9. Total Power for Reconfigurable FIR Filter employing different MAC‟s is shown in Fig.10.
Fig.9. Dynamic Power for Reconfigurable FIR Filter employing different MAC‟s
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Fig.10. Total Power for Reconfigurable FIR Filter employing different MAC‟s
Table 5. Leakage Power, Dynamic Power and Total Power Cadence Synthesis results for 4-tap RFIR filter
MAC
Leakage Power (nW)
Dynamic Power (nW)
Total Power (nW)
VMY –SQRT-CSLA 88082.218 668106.310 756188.528
VMY –SQRT-KSA 81816.932 660873.980 742690.912
VMY-SQRT-CSLA-BEC 77727.733 595124.159 672851.892
6.Conclusion
In this paper, implementation of VLSI architecture for 4-tap Reconfigurable FIR filter employing different MAC units is carried out using cadence tools. Reconfigurable FIR filter employing VMY-SQRT-CSLA-BEC achieves an area efficiency by 6.6% ,3.4%
when compared to VMY –SQRT-CSLA and VMY–SQRT-KSA. Reconfigurable FIR filter employing VMY-SQRT-CSLA-BEC achieves power improvement by 11.02%, 9.4
%when compared to VMY –SQRT-CSLA and VMY–SQRT-KSA. Thus RFIR Filter employing VMY-SQRT-CSLA-BEC is an area and power potent architecture.
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