MURDOCH RESEARCH REPOSITORY

MURDOCH RESEARCH REPOSITORY

http://dx.doi.org/10.1109/TEPM.2004.830516

Zhong, Z.W., Wong, K.W. and Shi, X.Q. (2004) Interfacial

behavior of a flip-chip structure under thermal testing. IEEE

Transactions on Electronics Packaging Manufacturing,

27 (1). pp. 43-48.

http://researchrepository.murdoch.edu.au/22765/

Copyright © 2004 IEEE

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Interfacial Behavior of a Flip-Chip Structure Under

Thermal Testing

Z. W. Zhong, K. W. Wong, and X. Q. Shi

Abstract—In this paper, the interfacial behavior of a flip-chip

structure under thermal testing was investigated using high sensitivity, real-time Moiré interferometry. The model package studied was a sandwich structure consisting of a silicon chip, epoxy underfill and FR4 substrate. The behavior of FR4-underfill and silicon-underfill interfaces of the specimen under certain thermal loading was examined. The results show that the shear strain variation increases significantly along the interfaces, with the maximum shear strain concentration occurring at the edge of the specimen. At the edge, the maximum shear strain occurs at the silicon-underfill interface, and the FR4-underfill interface experiences a slightly lower shear strain. The creep effect is more dominant in the FR4-underfill interface when the specimen is heated for 2 h at 100 C. Upon cooling to 20 C, both the interfaces of the specimen experience partial strain recovery.

Index Terms—Creep, flip chip, interfacial behavior, packaging,

real-time Moiré interferometry, shear strain, thermal stress, thermal testing.

I. INTRODUCTION

T

HE development of silicon-based integrated circuits has brought enormous revolution to modern technologies [1]. The evolution of different generations of personal computers was one of the major impacts [2]. Over the past two decades, there was an explosive growth in research and development efforts devoted to advance packaging technologies including flip-chip technology [3]–[7].

The current flip-chip technology relies heavily on underfill to increase its reliability. An underfill encapsulant reduces the effect of CTE (coefficient of thermal expansion) mismatch between the silicon chip and the substrate. It also protects the chip against moisture and impurities and makes the structure mechanically stronger. However, it also creates new reliability concerns. Delamination along the chip-underfill and substrate-underfill interfaces is a major reliability issue faced by flip-chip packages [8].

Improved reliability of solder bumped flip chips on FR4 sub-strate with a perfect underfill encapsulant has been confirmed by many researchers through thermal cycling tests, mechan-ical tests, shock and vibration tests and computational modeling [5], [9]–[11]. However, due to manufacturing processes such as fluxing, cleaning, dispensing and curing, underfill defects in the form of voids and cracks are quite common [12].

Z. W. Zhong and K. W. Wong are with the School of MPE, Nanyang Technological University, Singapore 639798, Singapore (e-mail: mzwzhong@ ntu.edu.sg).

X. Q. Shi is with the Singapore Institute of Manufacturing Technology, Sin-gapore 638075.

Digital Object Identifier 10.1109/TEPM.2004.830516

Design and testing of microelectronics devices usually involves stress analysis and fatigue life prediction. Finite element analysis has been used extensively to estimate stresses and strains in microelectronics packaging structures. Almost any kind of microelectronic devices can be modeled, but simplifications and uncertainties are inevitable due to complex loading and boundary conditions [13]–[17].

Therefore, advanced experimental techniques are in high de-mand to provide accurate solutions for deformation studies of microelectronics devices [18]. Validation of numerical models generated by the finite element method is achieved through ex-perimental measurements of the same quantities. Exex-perimental evaluations of stresses and strains usually provide realistic so-lutions because they are not affected by assumptions made to facilitate numerical procedures [19].

As the demand for better performance continues to shrink bump pitches and sizes of flip-chip packages, experimental techniques with high sensitivity and resolution are required to measure local strains and stresses. Real time observation is sometimes demanded to investigate the deformation trend and to understand the failure mechanism [20].

Optical Moiré interferometry has been used to analyze the thermal deformations and strains of electronics packages e.g., by Han and Post [21], Han and Guo [18], and Zhong et al. [22]. Recently, AFM (atomic force microscope) Moiré [23] and SEM (scanning electron microscope) Moiré [24] have also been employed to measure thermal strains of electronics packages. However, reports on measurements of thermal deformations and strains of electronics packages under thermal testing using real-time Moiré interferometry are still scarce [25].

In this paper, the interfacial behavior of a flip-chip structure under thermal testing was investigated using high sensitivity, real-time Moiré interferometry. The model package studied was a sandwich structure consisting of a silicon chip, epoxy under-fill and FR4 substrate. The behavior of underunder-fill-substrate and underfill-chip interfaces of the specimen under certain thermal loading was examined.

II. MOIRÉINTERFEROMETRY

Moiré interferometry is an optical experimental method with high spatial resolution and displacement sensitivity, providing noncontact in-plane measurements [26]–[28]. A high reflection, symmetrical diffraction grating is reproduced on the specimen surface. When loads are applied to the specimen, the specimen grating deforms together with the specimen surface. Two co-herent laser beams illuminate the specimen grating obliquely from angles and , creating interference and resulting in a virtual grating in the zone of their intersection. The virtual

44 IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, VOL. 27, NO. 1, JANUARY 2004

grating acts as the reference grating. The frequency of the ref-erence grating is given as

(1) where is the wavelength of the light source.

Both the virtual reference and the deformed specimen grat-ings interact with each other to form a Moiré fringe pattern, which can be viewed and photographed using a camera. The moiré pattern defining the displacement field is formed by in-teraction of the family of the specimen grating lines with the virtual reference grating. Similarly, the moiré pattern defining the displacement field is formed by interaction of the family of the specimen grating lines with the virtual reference grating [27]. For each point in the fringe pattern,

(2) (3) and are components of displacement in the and direc-tions respectively. and are fringe orders in the and field patterns respectively. The normal strains, and , and the shear strain can be determined by the following strain-dis-placement relationships.

(4) (5) (6) The Moiré interferometer used for real-time measurements of thermal deformations and strains of flip-chip specimens under thermal testing is shown in Fig. 1. It has several basic components such as a vibration-isolation optical table, a mini thermal-cycling chamber and a laser source to ensure its smooth operation. Mounting the interferometer onto the vi-bration isolation optical table could minimize vivi-brations. The mini thermal-cycling chamber provided the means to control the temperature of the specimen. The chamber was linked to a heater and the temperature within the chamber was displayed on the controller of the heater. A He-Ne laser was the light source for the Moiré interferometer. The laser had a wave-length of 633 nm.

III. EXPERIMENTALPROCEDURE

The specimens used in the experiments had a tri-material sandwich structure, consisting of a silicon die bonded to a FR4 substrate by a layer of underfill epoxy, as illustrated in Fig. 2. The silicon die was coated with a layer of passivation (0.3 ) and the surface of the FR4 substrate had a layer of solder mask (20 ). Solder joints were not included in the specimen be-cause it was reported [29] that solder joints played a small role in warping an underfilled flip-chip assembly while the underfill

Fig. 1. Moiré interferometer used for real-time measurements of thermal deformations and strains of flip-chip specimens under thermal testing.

epoxy played a dominant role. This understanding enabled us to simplify the assembly configuration for experimentation.

The specimen was slightly warped in the downward direction after the underfill was cured at 165 and cooled to 20 , due to the greater amount of contraction experienced by the FR4 substrate. This was reported before [19], [30]. However, the warpage was insignificant for our paper because relative but not absolute displacements were required for our strain analysis. A grating was replicated onto the cross-section surface of the specimen and cured for 24 h at room temperature. The frequency of the grating was 1200 lines/mm, which yielded an in-plane displacement resolution of 417 nm per fringe order.

Two different temperature profiles were used in the thermal testing of the specimens. The dwelling time at each of the tem-perature levels shown in Fig. 3 was 5 min. Dwelling time was necessary to ensure that the local temperature of the specimen had reached the same temperature as the chamber.

The other temperature loading profile used in the experiments is shown in Fig. 4. With this temperature profile, a specimen was exposed to two continuous thermal cycles. The specimen was heated for 2 h at a constant temperature of 100 and cooled for 1 h at a constant temperature of 20 . The purpose of having holding time at the minimum and maximum temperatures of the thermal cycle was to investigate the creep effect at the elevated temperature and strain recovery at room temperature.

The sample was mounted onto an aluminum stand and placed into the thermal chamber. Thermal grease was applied throughout the base of the stand to ensure better heat conduc-tivity from the chamber to the specimen. There was a need to calibrate the interferometer’s null field settings with the

Fig. 2. Schematic diagram of the specimen consisting of a silicon die bonded to a FR4 substrate by a layer of underfill epoxy.

specimen grating before a thermal cycling test was conducted. The initial null fields were captured by a CCD camera and recorded by a computer connected to the camera.

Excellent initial null fields were achieved after replication. The null fields appeared to have sparse fringes before thermal loading was applied. Actually, these initial fringes needed not be subtracted from the fringe patterns obtained after thermal loading was applied, as the Moiré fringe patterns exhibited a substantial large number of fringes and the subtraction was un-necessary to achieve the desired accuracy.

There was a heater connected to the thermal chamber for heating the specimen to the required temperature during the thermal cycling test. The cooling process for the thermal cy-cling was based on natural cooling.

Moiré fringe patterns of both the and displacement fields of the specimen, during thermal testing, were taken to perform a full-field analysis of the specimen. At least two pictures were taken for each Moiré fringe pattern to ensure that good fringe clarity was obtained. When the temperature of 100 was reached, the heater power was switched off in order for the thermal chamber to cool down to 20 . For the thermal test that required holding time at 100 for 2 h, the heater control remained powered on for 2 h before it was switched off.

IV. EXPERIMENTALRESULTS ANDDISCUSSION

A. Thermal Cycling Test Without Holding Time

The fringe patterns of the right half of the specimen were an-alyzed to determine the displacements, normal strains and shear strain along the silicon-underfill and FR4-underfill interfaces. Fig. 5 shows the - coordinates of the cross section surface of the specimen. The - coordinates are used to indicate the locations of the measured displacements and strains shown in Figs. 6–13.

The field (vertical) displacements measured along the sil-icon-underfill interface ( to 4 mm, ) and the FR4-underfill interface ( to 4 mm, ) during the thermal cycling test shown by Fig. 3 are plotted in Figs. 6 and 7, respectively. As temperature rose, the displacement mea-sured at each location along the interfaces increased. When the specimen was cooled down to 20 , there was plastic defor-mation in the specimen. At high temperatures and along one of the interfaces, the vertical displacement did not change much from the center to the location of . Subse-quently, the vertical displacement increased with increasing at high temperatures. The maximum displacement appeared at the

Fig. 3. Temperature profile (per one thermal cycle) without holding time at 100 and 20 C (see Fig. 4 for a temperature profile with holding time at 100 and 20 C).

Fig. 4. Temperature profile (per one thermal cycle) with 2-h and 1-h holding time at 100 and 20 C, respectively.

Fig. 5. x-y coordinates of the cross section surface of the specimen, used to indicate the locations of the measured displacements and strains shown in Figs. 6–13.

free edge . The bending displacement increased as temperature was raised. Upon cooling down to 20 , the ver-tical displacement along both interfaces was nearly uniform and the plastic deformation experienced by both interfaces was al-most the same.

The normal strains and shear strain along the silicon-under-fill interface and the FR4-undersilicon-under-fill interface of the specimen at 100 measured after the specimen was heated from 20 to

46 IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, VOL. 27, NO. 1, JANUARY 2004

Fig. 6. V field (vertical) displacements measured along the silicon-underfill interface (x = 0 to 4 mm, y = 0:5 mm) during the thermal cycling test shown by Fig. 3. The arrow% shows that the specimen is heated from 20 to 100 C, while the arrow. shows that the specimen is cooled from 100 to 20 C.

100 are presented in Figs. 8 and 9, respectively. The re-sults show clearly the variation in normal strains, and , and shear strain along the two interfaces. When the spec-imen was heated to 100 , increased gradually along the two interfaces toward the edge of the specimen. The variation in was not considerable along both interfaces. The variation in shear strain increased significantly along the interfaces, with the maximum shear strain concentration oc-curring at the edge of the specimen. This agrees with the previous findings [5], [31].

Based on this observation, the next interest of the measure-ments was focused on the edge of the specimen. Shear strain plot along the edge of the specimen is shown in Fig. 10, in order to assess the shear strain along the edge during the thermal cycling testing.

As shown in Fig. 10, shear strain along the edge of the spec-imen increases when the specspec-imen is heated, followed by sub-sequent shear strain decrease as the specimen is cooled. There is residual strain in the specimen when it is cooled down to 20 . The maximum shear strain occurs at the silicon-underfill inter-face ( , ), which is point A shown in Fig. 5. The FR4-underfill interface ( , ), which is point B shown in Fig. 5, experiences a slightly lower shear strain.

Fig. 11 shows the shear strain loops measured at point A ( , , the silicon-underfill interface at the specimen edge) and point B ( , , the FR4-underfill interface at the specimen edge) for one thermal cycle shown by Fig. 3. When the specimen is heated, points A and B deform as the shear strain increases with the thermal loading. As the specimen is cooled, both points A and B deform with residual strain. As a result, hysteresis loops are formed. The local CTE mismatch between the FR4 substrate and the underfill is relatively smaller as compared to the local CTE mismatch be-tween silicon and underfill. This causes the shear strain at point B to be smaller than that at point A.

Fig. 7. V field (vertical) displacements measured along the FR4-underfill interface (x = 0 to 4 mm, y = 0:8 mm) during the thermal cycling test shown by Fig. 3. The arrow% shows that the specimen is heated from 20 to 100 C, while the arrow. shows that the specimen is cooled from 100 to 20 C.

Fig. 8. Strains along the silicon-underfill interface (x = 0 to 4 mm, y = 0:5 mm) at 100 C measured after the specimen was heated from 20 to 100

C.

Fig. 9. Strains measured along the FR4-underfill interface (x = 0 to 4 mm, y = 0:8 mm) at 100 C measured after the specimen was heated from 20 to 100 C.

B. Thermal Cycling Test With Holding Time

The shear strain behavior of the interfaces with respect to holding time at an elevated temperature of 100 and at room temperature of 20 as shown in Fig. 4 was studied in this ex-periment. Figs. 12 and 13 show the shear strains for two thermal

Fig. 10. Shear strain along the specimen edge (x = 4 mm, y = 0:25 to 1.4 mm) during the thermal cycling test shown by Fig. 3. The arrow% shows that the specimen is heated from 20 to 100 C, while the arrow . shows that the specimen is cooled from 100 to 20 C.

Fig. 11. Shear strain loops for one thermal cycle measured at the silicon-underfill interface and the FR4-underfill interface.

Fig. 12. Shear strain measured at point A (x = 4 mm, y = 0:5 mm, the silicon-underfill interface at the specimen edge) for two thermal cycles using the temperature profile shown in Fig. 4.

silicon-underfill interface at the specimen edge) and point B ( , , the FR4-underfill interface at the specimen edge), respectively. The shear strains at the two points increased with holding time when the specimen was heated at a constant temperature of 100 for 2 h. This implied that creep

Fig. 13. Shear strain measured at point B (x = 4 mm, y = 0:8 mm, the FR4-underfill interface at the specimen edge) for two thermal cycles using the temperature profile shown in Fig. 4.

effect had taken place. The shear strain at point A experienced a 2% increase after the specimen was heated for 2 h at 100 . The shear strain at point B showed a 12% increase. This is an indica-tion that the creep effect is more dominant in the FR4-underfill interface. Upon cooling to 20 , the specimen experienced par-tial strain recovery as seen from the strain reduction at the two points after one hour of holding time at a constant temperature of 20 .

V. CONCLUSION

The interfacial behavior of the flip-chip structure and the creep effect on the specimen interfaces exposed to thermal cycling were studied using real-time Moiré interferometry. The findings were summarized as follows.

1) The displacements of both the silicon-underfill and FR4-underfill interfaces are similar. The displacement has a re-lationship with location, and the maximum displacement appears at the edge. As temperature rises, displacement at each location along the interfaces increases. When the specimen is cooled down to 20 , there is residual plastic deformation in the specimen.

2) increases gradually toward the edge of the spec-imen. The variation in is not considerable along the interfaces. The shear strain variation increases significantly along the interfaces, with the maximum shear strain concentration occurring at the edge of the specimen.

3) At the edge, the maximum shear strain occurs at the silicon-underfill interface. The FR4-underfill interface experiences a slightly lower shear strain.

4) At the edge, the shear strain at the silicon-underfill in-terface experienced a 2% increase after heated for 2 h at 100 , but the shear strain at the FR4-underfill inter-face showed a 12% increase. This is an indication that the creep effect is more dominant in the FR4-underfill in-terface. Upon cooling to 20 , both the interfaces of the specimen experienced partial strain recovery.

ACKNOWLEDGMENT

The authors would like to thank Dr. Z. P. Wang of the Singa-pore Institute of Manufacturing Technology for his cooperation.

48 IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, VOL. 27, NO. 1, JANUARY 2004

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Z. W. Zhong received the Dr.Eng. degree in

preci-sion engineering in 1989 from the Tohoku University, Sendai, Japan.

He then joined the Institute of Physical and Chemical Research, Saitama, Japan. He worked at the Gintic Institute of Manufacturing Technology, Singapore. He is currently with the Nanyang Technological University, Singapore. His research interests include electronics packaging; precision engineering and nanotechnology; mechatronics, design and control; biomedical engineering; and finite element modeling and analysis.

K. W. Wong received the B.E. degree (2nd Upper Hons) in mechanical

engi-neering from Nanyang Technological University, Singapore.

He is mainly involved in automation of equipment through SECS/GEM con-nectivity to increase machine uptime and improve yield.

X. Q. Shi has worked for more than 12 years in the

area of electronic packaging with Tsinghua Univer-sity, Beijing University of Aeronautics and Astronau-tics, City University of Hong Kong, and the Singa-pore Institute of Manufacturing Technology. He has published more than 50 international journal and con-ference papers. He is leading a team of Design for Manufacturability and Reliability with the Singapore Institute of Manufacturing Technology.