SC Filters

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Switched

Capacitor Filters

Franco Maloberti Franco Maloberti

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OUTLINE

•• SSwwiittcchheed cd caappaacciittoor tr teecchhnniqiquuee •• BBiiqquuaaddrraattiic c SSCC ﬁﬁlterslters

•• SSC C NN--ppaatthh ﬁﬁlterslters

•• FFininitite ge gaiain an and nd babandndwiwidtdth eh effffececttss •• LLaayyoouut t ccoonnssiiddeerraattiioonn

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SWITC

HED

CAPACITOR TECHNIQUE

•• AAn n aaccttiivvee fifilter is made of lter is made of op-amps, resistors and capacitors.op-amps, resistors and capacitors. •• TThhe e aaccccuurraaccy y oof f tthhee fifilter is determined by the accuracy of thelter is determined by the accuracy of the realized time costants since the capacitors and resitors are

realized time costants since the capacitors and resitors are realized by uncorrelated technological steps

realized by uncorrelated technological steps

•• In In CCMOMOS S tetechchnonolology gy ; ; ; ; hehencnce e ,, unacceptable f

unacceptable for most of or most of the applicationsthe applications •Hybrid realization with functional trimming •Hybrid realization with functional trimming •Problems f

•Problems for a or a fully integrated realizationfully integrated realization

δδττ τ τ ---     22 δδRR R R ---     22 δδCC C C ---     22 + + = = δδRR R ⁄ ⁄ R _≈_≈₄₀_40%_% _δδ_C_{C C} ⁄ ⁄ _C _≈_≈ ₃₀_30%_% δδττ τ τ --- ≈≈ 5050%%

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•• AccuracyAccuracy

•• Values of capacitors and resistors: for 70 nm oxide thickness 1Values of capacitors and resistors: for 70 nm oxide thickness 1 pF --> 2000 µ

pF --> 2000 µ22; 10 pF ; 10 pF is is a laa large rge capacicapacitance. tance. TTo geo gett τ τ = 10= 10-4-4 secsec R = 10

R = 1077 ΩΩ

The above problems are solved by the use of simulated resistors

made of switches and capacitors.

MOS technology is suitable because: MOS technology is suitable because:

•Offset free

•Offset free swswitchesitches •Good capacitors •Good capacitors •Satisf

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Simple SC structures Simple SC structures ∆ ∆Q = CQ = C₁₁ (V(V₁₁ - V- V₂₂) every) every ∆∆t = Tt = T 1 1 2 2 Φ Φ₁₁ ₂₂ II 1 1 2 2 C C 1 1 C C 1 1 II T T T T V V11 V_V22 V V11 V_V22 Φ Φ Φ Φ Φ Φ Φ Φ Φ Φ

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The two SC structures are The two SC structures are

(on average) equivalent to a resistor (on average) equivalent to a resistor

If the SC structures are used to get

If the SC structures are used to get an equivalent time constantan equivalent time constant τ τ_eq_eq = R= R_eq_eqCC₂₂ it results: it results: II V V11 V_V22 T T tt II ∆ ∆QQ ii∆∆tt VV11 –– VV22 R R ---TT = = == R R_e_eq_q TT C C₁₁ ---= = τ τ_e_eq_q TTCC22 C C₁₁ ---= =

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•• Its accuracy depends on the Its accuracy depends on the clock and on the capacitor matchingclock and on the capacitor matching accuracy

accuracy

•• IfIf τ τ_eq_eq=40 T C=40 T C₂₂ = 40 C= 40 C₁₁ (acceptable spread) regardless of the(acceptable spread) regardless of the value of

value of τ τ_eq_eq

A more complex SC structure: A more complex SC structure:

The charge is transferred twice per clock period T or we assume as The charge is transferred twice per clock period T or we assume as clock period half of the period of phases

clock period half of the period of phases ΦΦ₁₁ andand ΦΦ₂₂..

Φ Φ11 V V11 Φ Φ22 V V22 Φ Φ22 Φ Φ11 ∆ ∆QQ == 2C2C₁₁( ( VV₁₁ –– VV₂₂))

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SC

IN

TEG

RA

T

OR

Starting from the continuous-time circuit of the Integrator, we can Starting from the continuous-time circuit of the Integrator, we can ob-tain a SC integrator by replacing the continuous-time resistor with the tain a SC integrator by replacing the continuous-time resistor with the equivalent resistances. equivalent resistances. + + _ _ R R11 C C22

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Φ Φ11 Φ_Φ22 + + _ _ C C11 C C22 + + _ _ C C11 C C22 + + _ _ C C22 C C ₁₁ Φ Φ11 Φ Φ11 Φ Φ11 Φ Φ22 Φ Φ22 Φ Φ22 Φ Φ22 Φ Φ11 Φ Φ11 Φ Φ11

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•W

•We consider the e consider the samples of the input samples of the input and of the output and of the output taken attaken at the same times nT (the end of the sampling period).

the same times nT (the end of the sampling period).

•• Structure 1:Structure 1:

taking the z-transform: taking the z-transform:

V V_ou_o_utt[ [ ( ( nn ++11))TT]] VV_o_ou_utt( ( nnTT)) CC11 C C₂₂ ---VV_iin_n( ( nnTT)) – – = = V V_o_ou_utt( ( ))zz V V_in_in( ( ))zz ---C C₁₁ C C₂₂ ---1 1 z z –– 11 ---⋅⋅ – – = = V V_ou_o_utt[ [ ( ( nn ++11))TT]] VV_o_ou_utt( ( nnTT)) CC11 C C₂₂ ---VV_iin_n((nn ++ 11))TT]] – – = =

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Remember that for the continuous-time integrator: Remember that for the continuous-time integrator:

Comparing the sampled-data and continuous-time transfer functions we get: Comparing the sampled-data and continuous-time transfer functions we get:

V V_o_ou_utt( ( ))zz V V_in_in( ( ))zz ---C C₁₁ C C₂₂ ---z z z z –– 11 ---⋅⋅ – – = = V V_ou_o_utt[ [ ( ( nn ++ 11))TT]] VV_o_ou_utt( ( nnTT)) CC11 C C₂₂ ---{ { VV_in_in[ [ ( ( nn ++ 11))TT]]++ VV_in_in( ( nTnT))}} – – = = V V_o_ou_utt( ( ))zz V V_iin_n( ( ))zz ---C C₁₁ C C₂₂ ---z z ++ 11 z z –– 11 ---⋅⋅ – – = = V V_o_ou_utt( ( ))ss V V_iin_n( ( ))ss ---1 1 s sRR₁₁CC₂₂ ---– – = =

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FE

FE approapproximationximation

BE

BE approapproximationximation

Bilinear

Bilinear approapproximationximation

•It does not exist a simple SC integrator which implement the L •It does not exist a simple SC integrator which implement the LDD approximation.

approximation. •Note:

•Note: the cascade the cascade of a FE of a FE integrator and a BE iintegrator and a BE integrator isntegrator is equivalent to the cascade

equivalent to the cascade of two LD integrators.of two LD integrators.

R R₁₁ TT C C₁₁ --- ss 1 1 T T ---( ( zz –– 11)) → → → → R R₁₁ TT C C₁₁ --- ss 1 1 T T --- -z z –– 11 ( ( )) z z ---→ → → → R R₁₁ TT 2 2CC₁₁ --- ss 2 2 T T --- -z z –– 11 ( ( )) z z ++ 11 ( ( )) ---→ → → →

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•The ke

•The key point is to y point is to introduce a full peintroduce a full period delay from the input toriod delay from the input to the output the output Φ Φ11 _Φ22Φ + + _ _ Φ Φ22 Φ Φ11 + + _ _ C C22 C C11 C C11 C C22 '' ''

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•The same result is got with: •The same result is got with:

Φ Φ₁₁ ΦΦ₂₂ + + _ _ Φ Φ₂₂ _Φ_Φ₁₁ + + _ _ C C22 C C11 C C22 '' '' C C11

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STRA

Y INSENSITIVE

STRUCTURE

The considered SC integrators are sensitive to parasitics. The considered SC integrators are sensitive to parasitics.

Toggle structure: Toggle structure:

•• The top plate parasitic capacitance CThe top plate parasitic capacitance C_t,1_t,1 isis in parallel with C

in parallel with C₁₁

•• It is not negligible with respect to CIt is not negligible with respect to C₁₁ andand it is non linear

it is non linear

•• The top plate parasitic capacitance CThe top plate parasitic capacitance C_t,1_t,1 acts as a toggle structure

acts as a toggle structure

Bilinear resistor: Bilinear resistor: Φ Φ₁₁ ΦΦ₂₂ C C11 C Ct,1t,1 C_Cb,1_b,1 Φ Φ₁₁ Φ Φ₂₂ C C11 C Ct,1t,1 C_Cb,1_b,1

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•• Both the parasiticBoth the parasitic capacitances C

capacitances C_t,1_t,1, C, C_b_b,1_,1 actact as

as toggle toggle structures. structures. TheirTheir values are different (of a values are different (of a factor

factor ≈≈ 10) and they are non10) and they are non linear.

linear.

•• StraStray insensitivity can be y insensitivity can be gotgot for the

for the ﬁﬁrst two structures ifrst two structures if one terminal is switched one terminal is switched between points at the same between points at the same voltage.

voltage.

•• The right-side parasiticThe right-side parasitic capacitor is switched capacitor is switched

between the virtual ground between the virtual ground and ground (note: even in and ground (note: even in DC

DC VV_v.g._v.g. must equal Vmust equal V_ground_ground))

Φ Φ11 Φ Φ11 Φ Φ22 Φ Φ22 C C11 C Ct,1t,1 C Cb,1b,1 C C11 Φ Φ₁₁ Φ Φ₂₂ Φ Φ₁₁ Φ Φ₂₂ Virtual Virtual ground ground C C11 Φ Φ₁₁ Φ Φ₂₂ Virtual Virtual ground ground Φ Φ₂₂ Φ Φ₁₁

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•• The left side capacitor is connected, The left side capacitor is connected, during phase 1, to a during phase 1, to a voltagevoltage (or equivalent) source.

(or equivalent) source.

•• The charge injected into virtual ground is important, not the oneThe charge injected into virtual ground is important, not the one furnished by the input source.

furnished by the input source.

•• Structure A is equivalent to the toggle structure, but the injectedStructure A is equivalent to the toggle structure, but the injected charge has opposite sign.

charge has opposite sign.

•• Equivalent negative resistance allows to implement Equivalent negative resistance allows to implement non invnon inverertingting integrators.

integrators.

•• It is It is possible to easily realize a stpossible to easily realize a straray insensitive bilinear resistory insensitive bilinear resistor with fully differential con

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SC BIQUADRATIC

FILTERS

Consider a (continuous-time) biquadratic transfer function Consider a (continuous-time) biquadratic transfer function

If the bilinear transformation is applied, it results a z-biqu

If the bilinear transformation is applied, it results a z-biquadratic trans-adratic trans-fer function

fer function

where the coefficients are: where the coefficients are:

H H s( ( ))s pp00 sspp11 ss 2 2 p p₂₂ + + ++ s s22 ssωω00 Q Q₀₀ --- ωω₀₀ 2 2 + + ++ ---= = H H s( ( ))s aa00 zzaa11 zz 2 2 a a₂₂ + + ++ b b₀₀ ++zzbb₁₁ ++zz22bb₂₂ ---= = a a₀₀ pp₀₀ 22 T T ---pp₁₁ – – 44 T T22 ---pp₂₂ + + = =

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a a₁₁ 22pp₀₀ 88 T T22 ---pp₂₂ – – = = a a₂₂ pp₀₀ 22 T T ---pp₁₁ 4 4 T T22 ---pp₂₂ + + ++ = = b b₀₀ ωω₀₀22 22 T T --- -ω ω₀₀ Q Q ---– – 44 T T22 ---+ + = = b b₁₁ 22ωω₀₀22 88 T T22 ---– – = = b b₂₂ ωω₀₀22 22 T T --- -ω ω₀₀ Q Q ---4 4 T T22 ---+ + ++ = =

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All the stable z-biquadratic transfer functions

All the stable z-biquadratic transfer functions are realized by the topology:are realized by the topology:

+ + --+ + --G G D D E E C C A A B B F F II JJ H H 1 1 F F11 F F22 V Vinin tt V V0101 V V0202

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Features:

•Loop of two integrators one inv

•Loop of two integrators one invererting and the other ting and the other noninvnoninvererting.ting. •Damping around the loop

•Damping around the loop provided by capacitor F or (and)provided by capacitor F or (and) capacitor E (usually only E or F are included in the network). capacitor E (usually only E or F are included in the network). •Two outputs available V

•Two outputs available V_0,1_0,1 VV_0,2_0,2..

•Denominator of the transfer function determined by the capacitors •Denominator of the transfer function determined by the capacitors along the loop (A, B, C, D, E, F).

along the loop (A, B, C, D, E, F).

•Transmission zeros (numerator) realized by the capacitors (G, H, •Transmission zeros (numerator) realized by the capacitors (G, H, I, J).

I, J).

•Input signal sampled during

•Input signal sampled during ΦΦ₁₁ and held for a full clock periodand held for a full clock period •Charge injected into the virtual ground during

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Charge conservation equations: Charge conservation equations:

DV

DV_0,1_0,1(n+1) = DV(n+1) = DV_0,1_0,1(n) - GV(n) - GV_in_in(n+1) + HV(n+1) + HV_in_in(n) - CV(n) - CV_0,2_0,2(n+1) - E[V(n+1) - E[V_0,2_0,2(n+1) - V(n+1) - V_0,2_0,2(n)](n)] (B + F)V

(B + F)V_0,2_0,2(n+1) = BV(n+1) = BV_0,2_0,2(n) + AV(n) + AV_0,1_0,1(n) - IV(n) - IV_in_in(n+1) + JV(n+1) + JV_in_in(n)(n)

Taking the z-transform and solving, it results: Taking the z-transform and solving, it results:

•• 10 Capacitors10 Capacitors

•• 6 Equations a6 Equations a₀₀, a, a₁₁, a, a₂₂, b, b₀₀, b, b₁₁, b, b₂₂

•• Dynamic range optimizationDynamic range optimization H H₁₁ VV00 1,,1 V V_iin_n ---IICC ++IIEE –– GGFF–– GGBB ( ( ))zz22 ++ ( ( FHFH ++BHBH ++ BBGG J–– JCC –– JEJE –– IIEE))zz ++( ( EJEJ –– BHBH)) D DBB ++ DDFF ( ( ))zz22 ++( ( AACC ++AEAE –– 2D2DBB ––DDFF))zz ++ ( ( DBDB –– AEAE)) --- -= = == H H₂₂ VV00 2,,2 V V_iin_n ---D DIIzz22 ++ ( ( AGAG –– DDII –– DDJJ))zz ++ ( ( DDJJ –– AAHH)) D DBB ++ DDFF ( ( ))zz22 ++( ( AACC ++AEAE –– 2D2DBB ––DDFF))zz ++ ( ( DBDB –– AEAE)) --- -= = ==

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•• Scaling for minimum total capacitance in the groups of capacitorsScaling for minimum total capacitance in the groups of capacitors connected to the virtual ground of the op-amp

connected to the virtual ground of the op-amp₁₁ and the op-ampand the op-amp₂₂..

•• Since there are 9 conditions, one capacitor can be set equal toSince there are 9 conditions, one capacitor can be set equal to zero

zero

E

E = = 00 ““F F ttyyppee”” F

F = = 00 ““E E ttyyppee””

Firstly the 6 equations are satisfied. Later capacitors D and A Firstly the 6 equations are satisfied. Later capacitors D and A are adjusted in order to optimize the dynamic range. Finall

are adjusted in order to optimize the dynamic range. Finally ally all the capacitor connected to the virtual ground of the op-amp are the capacitor connected to the virtual ground of the op-amp are normalized to the smaller of the group.

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Scaling for minimum total capacitance Scaling for minimum total capacitance

Assume that C

Assume that C₃₃ is the smallest capacitance of the group. In order to makeis the smallest capacitance of the group. In order to make minimum the total capacitance C

minimum the total capacitance C₃₃ must be reduced to the smallest value al-must be reduced to the smallest value al-lowed by the technology (C

lowed by the technology (C_min_min))

•• Multiply all the capacitors Multiply all the capacitors of the group byof the group by

+ + _ _ C C22 C C11 C C33 C C44 C Cnn k k CCmimi nn C C₃₃ ---= =

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SC LADDER FILTERS

Orchard’s observation

Doubly-terminated LC ladder network that are designed to effect Doubly-terminated LC ladder network that are designed to effect max-imum power transfer from source to load over the

imum power transfer from source to load over the filter passband fea-filter passband fea-ture very low sensitivities to value component variation.

ture very low sensitivities to value component variation. Syntesis of SC Ladder Filters:

Syntesis of SC Ladder Filters:

Symple approach Symple approach

•• Replace evReplace every ery resistance Rresistance R_ii in an active ladder structure with ain an active ladder structure with a switched capacitor C

switched capacitor C_ii = T/R= T/R_ii..

•• Use a full clock period Use a full clock period deladelay along all the ty along all the two integrator loop (itwo integrator loop (it results automatically veri

results automatically veriﬁﬁed in single ended schemes).ed in single ended schemes). It results an LD equivalent, except for the terminations.

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Quasi LD transformation:

Prewarp the specifications using sin(

Prewarp the specifications using sin(ωωT/2)T/2)

A A t t t t e e n n u u a a t t i i o o n n

w w w wsbsb w wpbpb A Apbpb A A t t t t e n e n u u a a t t i i o o n n

w w w w w w A Apbpb A Asbsb PREWARPED SPECIFICATION PREWARPED SPECIFICATION sin(

sin( _pb_{pb T/2)}T/2) sin(sin( _sb_{sb T/2)}T/2)





A_Asb_sb DESIRED SPECIFICATION DESIRED SPECIFICATION



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Effect of the terminations:

if R

if R₁₁ = T/ C= T/ C₁₁ and Rand R₃₃ = T/C= T/C₃₃ we get:we get:

+ + _ _ R R11 R R C C22 _ _ + + _ _ C C22 C C11 C C33 H H_D_DII( ( ))ss RR33 s sCC₂₂RR₁₁RR₃₃ ++ RR₁₁ ---= = HH_D_DII( ( ))ss CC11 s sTTCC₂₂ ++ CC₃₃ ---= = V

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Taking the z-transform we get: Taking the z-transform we get:

along the unity circle z=e along the unity circle z=e j jωωTT

The half clock period delay will be used in the cascaded integrator in The half clock period delay will be used in the cascaded integrator in order to get the LD transformation

order to get the LD transformation

•• The termination is complex and frequency dependent.The termination is complex and frequency dependent.

•• The integrating capacitor CThe integrating capacitor C₂₂ must be replaced by Cmust be replaced by C₂₂ + C+ C₃₃ /2. /2. z

zVV_o_ou_utt( ( CC₂₂ ++ CC₃₃)) == CC₂₂VV_o_ou_utt++ CC₁₁VV_iin_n

H H_D_DII( ( ))zz CC11 C C₂₂( ( zz –– 11)) ++zzCC₃₃ --- -C C₁₁zz––11 2 ⁄ ⁄ 2 C C₂₂( ( zz11 2 ⁄ ⁄ 2 –– zz––1 21 ⁄ ⁄ 2)) ++zz11 2 ⁄ ⁄ 2CC₃₃ --- -= = == H H_DII_D ( ( ee j jωωTT)) CC11ee j j – – ωωTT 2 ⁄ ⁄ 2 C C₂₂( ( ee j jωωTT 2 ⁄ ⁄ 2 –– ee–– j jωωTT 2 ⁄ ⁄ 2)) ++ ee j jωωTT 2 ⁄ ⁄ 2CC₃₃ --- --C C₁₁ee–– j jωωTT 2 ⁄ ⁄ 2 2 2jj C( ( C₂₂ ++ CC₃₃)) ωωTT 2 2 --- CC33 ω ωTT 2 2 ---cos cos + + sin sin ---= = ==

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Complex termination:

Note: the output voltage changes during Note: the output voltage changes during ΦΦ

Taking the z-transform: Taking the z-transform:

+ + _ _ C C22 C C11 C C33 F F11 V V_o_ou_utt( ( nn ++ 11))CC₂₂ VV_o_ou_utt( ( ))nn CC22 2 2 C C₂₂ ++ CC₃₃ --- ++ CC₁₁VV_iin_n( ( ))nn = = z zVV_o_ou_uttCC₂₂ VV_o_ou_utt CC₂₂ CC22CC33 C C₂₂ ++CC₃₃ ---– –       _C_C 1 1VViinn + + = =

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along the unity circle z=e along the unity circle z=e j jωωTT

•• The imaginary part of the contribution of the termination isThe imaginary part of the contribution of the termination is negative

negative

•• The The integrating integrating capacitor capacitor must must be be replaced replaced byby H H_D_DII( ( ))zz CC11 C C₂₂( ( zz –– 11)) CC22CC33 C C₂₂ ++CC₃₃ ---+ + ---C C₁₁zz––11 2 ⁄ ⁄ 2 C C₂₂( ( zz1 21 ⁄ ⁄ 2 –– zz––11 2 ⁄ ⁄ 2)) zz––11 ⁄ ⁄ 22 CC22CC33 C C₂₂ ++CC₃₃ ---+ + --- -= = == H H_DII_D ( ( ee j jωωTT)) CC11ee j j – – ωωTT 2 ⁄ ⁄ 2 2 2jj CC₂₂ 11 2 2 --- -C C₂₂CC₃₃ C C₂₂ ++CC₃₃ ---– –       ωωTT 2 2 ---C C₂₂CC₃₃ C C₂₂ ++CC₃₃ ---ω ωTT 2 2 ---cos cos + + sin sin --- -= = C C₂₂ CC₂₂ 11 2 2 --- -C C₂₂CC₃₃ C C₂₂ ++CC₃₃ ---– –

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Example: 5th order filter Example: 5th order filter

Passive prototype Passive prototype Flow diagram Flow diagram SC implementa-SC implementa-tion tion V Vinin R RSS C C11 C_C33 C_C55 L L22 L_L44 R R66 IISS II44 II22 V V11 V_V33 V_V55 VVoutout II66 R/R R/Rss 1/s 1/s 1/s 1/s 1/s1/s 1/s1/s + + __ __ __ __ __ __ + + ++ ++ ++ ++ ++ R/R R/R66 V Vinin VV11 VV33 VV55 V V66 V V44 V V22 V Vss τ τ₁₁ 1/s1/s τ τ22 τ_τ33 _ττ44 ττ55 _ _ __ __ __ __ __ _ _ _ _ __ _ _ + + - - + + - + + - - + + - + + - -1 1 11 1 1 11 1 1 11 τ τ₁₁ T T τ τ₃₃ T T τ τ₂₂ T T τ τ₄₄ T T τ τ₅₅ T T

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FINITE GAIN AND

BANDWIDTH EFFECT

If the op-amp has finite gain A

If the op-amp has finite gain A₀₀ the “virtual ground” voltage is Vthe “virtual ground” voltage is V₀₀ /A /A₀₀

z-transforming: z-transforming: + + _ _ C C22 C C11 C C₂₂VV₀₀( ( nn ++11)) 11 11 A A₀₀ ---+ +       _C_C 2 2VV00( ( ))nn 11 1 1 A A₀₀ ---+ +       _C_C 1 1 VViinn( ( nn ++ 11)) V V₀₀( ( nn ++11)) A A₀₀ ---+ + – – = = H H z( ( ))z VVoo( ( ))zz V V_iin_n( ( ))zz ---C C₁₁zz C C₂₂ 11 11 A A₀₀ ---+ +      ₍₍_z_z _–_– ₁₁₎₎ CC11 A A₀₀ ---zz + + --- -– – = = ==

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Comparing H(z) with the transfer function with Comparing H(z) with the transfer function with

Substituting z = e

Substituting z = esTsT, on the imaginary axis, on the imaginary axis

Magnitude error Magnitude error Phase error Phase error A A₀₀ →→ ∞∞ H H_iid_d( ( ))zz CC11zz C C₂₂( ( zz –– 11)) ---– – = = H H z( ( ))z H H_iid_d( ( ))zz 1 1 11 A A₀₀ ---+ +       CC11 C C22AA00 ---z z z z––11 ---+ + ---H H_iid_d( ( ))zz 1 1 11 A A₀₀ ---+ +       CC11 C C22AA00 ---1 1 z z––11 ---1 1 2 2 --- -1 1 2 2 --- -+ + ++       + + ---H H_iid_d( ( ))zz 1 1 11 A A₀₀ ---1 1 2 2 --- -C C₁₁ C C₂₂AA₀₀ ---+ + ++          CC₁₁ 2 2CC₂₂AA₀₀ ---z z++ 11 z z––11 ---+ + ---= = == == H H e( ( e j jωωTT)) HHiidd ee j jωωTT ( ( )) 1 1 11 A A00 ---C C₁₁ 2 2C_C22AA00 --- j j C C₁₁ 2

2C_C22AA00_tan_tan( ( ωωTT 2 ⁄ ⁄ 2))

---– – + + ++ ---H H_iid_d( ( ee j jωωTT)) 1 1 –– mm( ( ))ωω –– j jθ θ ω( ( ))ω ---= = == m m( ( ))ωω 11 A A₀₀ --- 11 C C₁₁ 2 2C_C22 ---+ +          – – = = θ θ ω( ( ))ω CC11 ω ω ---C C₁₁ ω ω ---≅ ≅ = =

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For the noninverting integrator For the noninverting integrator

z-transforming and solving z-transforming and solving

Same magnitude and phase error result Same magnitude and phase error result

+ + _ _ C2 C2 C1 C1 C C₂₂VV₀₀( ( nn ++11)) 11 11 A A₀₀ ---+ +       _C_C 2 2VV00( ( ))nn 11 1 1 A A₀₀ ---+ +       _C_C 1 1 VViinn( ( ))nn V V₀₀( ( nn ++ 11)) A A₀₀ ---+ + + + = = H H z( ( ))z VVoo( ( ))zz V V_in_in( ( ))zz ---C C₁₁ C C₂₂ 11 11 A A₀₀ ---+ +      ₍₍_z_z _–_– ₁₁₎₎ CC11 A A₀₀ ---zz + + --- -= = ==

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FULLY DIFFERENTIAL CIRCUITS

•Fully differential con

•Fully differential conﬁﬁgurations reduce the gurations reduce the clock fclock feedthrougheedthrough noise and increase the dynamic range.

noise and increase the dynamic range. •They allow an increase design

•They allow an increase design ﬂﬂexibilityexibility

Simple integrator (inverting and non inverting) Simple integrator (inverting and non inverting)

+ + _ _ C C22 C C11 Φ Φ₁₁ Φ Φ₂₂ Φ Φ₂₂ Φ Φ₁₁ Φ Φ₂₂ ((ΦΦ₂₂₎₎ ((ΦΦ1)1)

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Immediate sampling (inverting and non inverting) integrator: Immediate sampling (inverting and non inverting) integrator:

Delayed sampling (inverting and non inverting) integrator: Delayed sampling (inverting and non inverting) integrator:

Φ Φ₁₁ + + _ _ Φ Φ₁₁ Φ Φ₂₂ Φ Φ₂₂ Φ Φ₁₁ Φ Φ₁₁ Φ Φ₂₂ Φ Φ₂₂ V Vinin -V -Vinin -V -Vinin V Vinin Φ Φ₁₁ Φ Φ₁₁ Φ Φ₁₁ + + _ _ Φ Φ₁₁ Φ Φ₂₂ Φ Φ₂₂ Φ Φ₁₁ Φ Φ₁₁ Φ Φ₂₂ Φ Φ₂₂ V Vinin -V -Vinin -V -Vinin V Vinin ΦΦ22 Φ Φ₂₂

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•It is possible to reduce the o

•It is possible to reduce the op-ampp-amp ﬁﬁnite bandwidth dependencenite bandwidth dependence by the use of delay

by the use of delayed sampling inverting and ed sampling inverting and non invnon inverertingting integrators along a second

integrators along a second order loop.order loop.

Φ Φ11 + + Φ Φ₁₁ Φ Φ₂₂ Φ Φ₂₂ Φ Φ11 Φ Φ11 Φ Φ₂₂ Φ Φ₂₂ Φ Φ₂₂ ΦΦ₂₂ Φ Φ₂₂ Φ Φ₂₂ Φ Φ₁₁ _Φ11Φ Φ Φ₁₁ ΦΦ11 + + _ _ _ _

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•The peaking in the frequency response due to the phase error is •The peaking in the frequency response due to the phase error is strongly reduced

strongly reduced •It is easy to reali

•It is easy to realize bilinear integratorsze bilinear integrators

Φ Φ11 + + Φ Φ11 Φ Φ₂₂ Φ Φ₁₁ Φ Φ₁₁ ΦΦ22 V Vinin V Vinin Φ Φ₂₂ Φ Φ22 C C22 C C11 C C22 C C11 _ _ _ _

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NOISE IN SC

CIRCUI

TS

The noise sources in a SC

The noise sources in a SC network are:network are:

•• Clock feedthrough noiseClock feedthrough noise

•• Noise coupled from power supply lines and substrateNoise coupled from power supply lines and substrate

•• kT/C noisekT/C noise

•• Noise generators of the op-ampNoise generators of the op-amp

The first two sources are the

The first two sources are the same as in mixed analog-digital circuits.same as in mixed analog-digital circuits. kT/C noise:

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Consider the simple network: Consider the simple network:

In the “on” state the switch can be In the “on” state the switch can be modeled with a noisy resitor

modeled with a noisy resitor

Noise equivalent circuit: Noise equivalent circuit:

The white spectrum of the “on” resistance is shaped by the low pass The white spectrum of the “on” resistance is shaped by the low pass

v vinin C C S1 S1 4 4kkTTR R f f CC S1 S1 on on R Ronon

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action of the R

action of the R_on_onC filter.C filter.

The noise voltage across the capacitor C has spectrum: The noise voltage across the capacitor C has spectrum:

When the switch is turned “off” the noise voltage v

When the switch is turned “off” the noise voltage v_n,c_n,c is sampled andis sampled and held onto C held onto C S S_n,c_n_,c vv2_n_{n c}2_,,_c 4kTR4kTR_o_on_n HH ff( ( )) 22∆∆ff 4kTR4kTRoonn∆∆ff 1 1 ++ ( ( 22ππffRR_o_on_nCC))22 ---= = == == f f S S

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The folding of the spectrum in band-base gives a white spectrum. The folding of the spectrum in band-base gives a white spectrum.

It power (the dashed area) is equal to the integral of S It power (the dashed area) is equal to the integral of S_n,c_n,c

Procedure for the noise calculation in SC networks: Procedure for the noise calculation in SC networks:

f f v v n,cn,c f f CKCK /2 /2 ** v v_n_{n c}22_,,_c 4kTR4kTRoonn∆∆ff 1 1 ++ ( ( 22ππffRR_o_on_nCC))22 ---0 0 ∞ ∞ ∫ ∫ ddff 44kkTT 2 2ππCC ---( ( atanatanxx))₀₀ ∞ ∞ kkTT C C ---= = == ==