Power Electronics - MIT

Chapter 1

Introduction and Analysis Methods

1.1 Switching Power Electronics

Read Chapter 1 of “Principles of Power Electronics” (KSV) by J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Addison-Wesley, 1991.

Linear Regulator io + Vx − + − + Vin Vo −

Figure 1.1: Linear Regulator

Control vx such that Vo = Vo,REF : Simple, accurate, high-bandwidth, but 1

Pdiss = < vxio > > 0 (1.1) Pout η = Pin Voio = Vinio Vo = (1.2) Vin @ Vin = 15v, Vo = 5v→ η = 33% (1.3)

For efficiency we will consider switching power converters: q(t) − + _Vo Vin 0 1 q(t) + DT T v(t) <Vo> = dVin −

Figure 1.2: Considering Switching Power Convertor

Add filtering:

NOTE: Only lossless elements. L, C (energy storage).

Use semiconductors as switches. Switches: Block V, carry I, but NOT at the same time!

1.2. ANALYSIS TECHNIQUES 3 − + + + − + Vin Vo Vx − _v(t) − Vx <Vo> ~ dVin + + Vin Vo − −

Figure 1.3: Add Filtering

1.2 Analysis Techniques

1.2.1 Methods of Assumed States

Semiconductor switches are typically not fully controllable. Let’s consider how to analyze a switching circuit in time domain:

Simple Rectifier

Example: (trivial but fundamental)

Vd + − id + Vo VsSin(ωt) −

Figure 1.4: Simple Rectifier Diodes: Uncontrolled

• Cannot sustain negative Current (will turn off)

id

Vd

Figure 1.5: Diode

The method of assumed states allows us to figure out which un/semi-controlled switches are on as a function of time.

1. Assume a state (on/off) for all un/semi-controlled switches.

2. Calculate voltages and currents in the system (linear circuit theory).

3. See if any switch conditions are violated (e.g., “on” diode has negative current and “off” diode has positive voltage.)

4. If no violations, then done, else if violation assume a new set of states go back to step 1. Vd + − id + Vo VsSin(ωt) −

1.2. ANALYSIS TECHNIQUES 5

• If Vs sin(ωt) > 0 and we assume diode off: vd > 0, since this is not possible diode must be on during this condition.

• If Vs sin(ωt) < 0 and we assume diode on: id < 0, since this is not possible diode must be off during this condition.

Vs sin(ωt) > 0 → diode on:

+ Vo VsSin(ωt)

−

Figure 1.7: Simple Rectifier with Diode On Vs sin(ωt) < 0 → diode off:

+ Vo VsSin(ωt)

−

Figure 1.8: Simple Rectifier with Diode Off

Vs π Vo VsSin( t) <Vo> = t ω ω ω π 2π i=(VsSin( t))/R

Figure 1.9: Rectifier Waveform Very simple example but principle works in general.

1.2.2 Periodic Steady State

In power electronics we are often interested in the periodic steady state. In periodic steady state the system returns to the same point at the end of cycle (beginning matches end), so things are operating cyclicly.

In periodic steady state (P.S.S.):

di V = L dt di < V > = < L > dt di = L < > dt di since < >= 0 < V > = 0 (1.4) dt → Therefore, in P.S.S.: Inductor < VL >= 0 average diL = 0 • → dt Capacitor < VC >= 0 average dV _dt C = 0 • →

The P.S.S. conditions are useful for analysis. Consider adding a filter to smooth the ripple current in our simple rectifier:

VsSin( t) + Vo VL + + Vd + Vx ω − − − −

Figure 1.10: Simple Rectifier with Filter

1.2. ANALYSIS TECHNIQUES 7 VL + − + Vo VsSin(ωt) −

Figure 1.11: Simple Rectifier with Filter and Diode On

Vs sin(ωt) − VL − vo = 0

< Vs sin(ωt) > = 0 in P.S.S. < VL > = 0 in P.S.S.

vo = 0 (1.5)

If diode were always on < Vo >= 0 and io must be < 0 part of the time. We know diode must turn off during part of cycle by the method of assumed states. What happens: ω VsSin( t) ω π 2 π t io Vx

Figure 1.12: Rectifier with Filter Waveform

Negative voltage for part of cycle drives i _→ 0. Exact analysis in KSV, Section 3.2.2. Good for review of time-domain analysis.

Main point: Method of assumed states and P.S.S. condition are useful tools to determine system behavior.

Now, in P.S.S. < Vx >=< Vo >, since < VL >= 0. < Vx > is pos 1₂ sin plus some neg 1

2 sin, so we lose some voltage as compared to a pos 1 2 sin. Solution: Free-wheeling diode _→ Half-wave Rectifier.

Vd VL + - + ­ D1 _io + + Vo VsSin(ωt) D2 Vx

-Figure 1.13: Simple Rectifier with Free Wheeling Diode D2 clamps so that Vx never goes negative. io “free-wheels”.

Using method of assumed states: • D1 conducts when Vs sin ωt > 0. • D2 conducts when Vs sin ωt < 0.

2π π Io = ω t ω Vx VsSin( t) R V0

Figure 1.14: Rectifier with Free Wheeling Diode Waveform

< VL > = 0 in P.S.S. < Vo > = < Vx > = 1 2π Z π 0 Vs sin(φ)dφ

X

1.2. ANALYSIS TECHNIQUES 9

Vs

= (1.6)

π

NOTE: This circuit is rarely used in line applications today for several reasons, but the analysis technique is the key point. Full-wave rectifier is more common.

NOTE: For analyzing output current, output voltage, etc., we can do an equivalent-source replacement. Linear circuit with sum of fourier equivalent-sources.

io Veq(t) + Vo Veq(t) -t

Figure 1.15: Linear Circuit with Sum of Fourier Sources

∞ Veq = Bn cos(nωt + φn) (1.7) n=0 vo(ω) X If H(ω) = Vo = H(nω) Bn cos(nωt + φn+ < H(nω)) (1.8) vx(ω) ⇒ n | |

Main point: We can replace difficult to handle part of circuit with an equivalent voltage source, then use linear circuit theory to analyze from there.

Summary of analysis thechniques: Method of assumed states •

• Periodic Steady State

Introduction to Rectifiers

Read Chapter 3 of “Principles of Power Electronics” (KSV) by J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Addison-Wesley, 1991.

Start with simple half-wave rectifier (full-bridge rectifier directly follows).

Ld + − Id Vx D1 _id + + _{ω t} Vo VsSin(ωt) D2 Vx π 2π − − VsSin(ωt) D1 ON D2 ON

Figure 2.1: Simple Half-wave Rectifier

In P.S.S.: < vo > = < vx > vs = (2.1) π 10

2.1. LOAD REGULATION 11 vs If Ld Big → id ≃ Id = πR (2.2) If L_R d ≫ 2 ω π

⇒ we can approximate load as a constant current.

2.1 Load Regulation

.

Now consider adding some ac-side inductance Lc (reactance Xc = ωLc).

• Common situation: Transformer leakage or line inductance, machine winding inductance, etc.

• Lc is typically ≪ Ld (filter inductance) as it is a parasitic element.

Lc Ld D1 + R VsSin(ωt) D2 Vx −

Figure 2.2: Adding Some AC-Side Inductance

Assume Ld ∼ ∞ (so ripple current is small). Therefore, we can approximate load as a “special” current source.

vx

“Special” since < vL >= 0 in P.S.S. ⇒ Id =< > (2.3) R

Assume we start with D2 conducting, D1 off (V sin(ωt) < 0). What happens when V sin(ωt) crosses zero?

i1 Lc

D1

VsSin(ωt) D2 i2 Id

Figure 2.3: Special Current • D1 off no longer valid.

But just after turn on i1 still = 0. • Therefore, D1 switches from D2 and D2 to D1. are both on d Lc

uring a commutation period, where current

i1 D1 + VsSin( ω t) D2 Vx _Id _ i2

Figure 2.4: Commutation Period D2 will stay on as long as i2 > 0 (i1 < Id).

Analyze: di1 1 = Vs sin(ωt) dt Lc Z ωt V s i1(t) = sin(ωt)d(ωt) 0 ωLc Vs 0 = ωLc cos(Φ)|ωt Vs = [1 _{− cos(ωt)]} (2.4) ωLc

2.1. LOAD REGULATION 13 i1 u Id t ω

Figure 2.5: Analyze Waveform Commutation ends at ωt = u, when i1 = Id.

Commutation Period:

Vs ωLcId

Id =

ωLc [1 − cos u] ⇒ cos u = 1 − Vs

(2.5) As compared to the case of no commutating inductance, we lose a piece of output voltage during commutation. We can calculate the average output voltage in P.S.S. from < Vx >: 1 Z π < Vx > = Vs sin(Φ)dΦ 2π u Vs = [cos(u) + 1] 2π ωLcId

f rom bef ore cos(u) = 1 − _V

s XcId = 1 − _V s Vs ωLcId < Vx > = [1 − ] (2.6) π Vs

So average output voltage drops with: 1. Increased current

π u VsSin(wt) Vx ω t π+u 2 π 2 i1 Id ω t u +u 2 +u D1 D2 π π 2π π D1+D2

Figure 2.6: Commutation Period 2. Increased frequency

3. Decreased source voltage

We get the “Ideal” no Lc case at no load.

We can make a dc-side thevenin model for such a system as shown in Figure 2.7. No actual dissipation in box: “resistance” appears because output voltage drops when current increases.

This Load Regulation is a major consideration in most rectifier systems. • Voltage changes with load.

2.1. LOAD REGULATION 15 Id + <Vx> <Vx> Id 2 π slope 2 π Lc ω ω Lc 2Vs Lc ω − + − π Vs − π Vs

Figure 2.7: DC-Side Thevenin Model

All due to non-zero commutation time because of ac-side reactance. occurs in most rectifier types (full-wave, multi-phase, thyristor, etc.). rectifier has similar problem (similar analysis).

Read Chapter 4 of KSV. This effect Full-bridge + <Vx> D3 D2 D1 D4 ω VsSin( t) Lc 2Vs π Full−Bridge Vs Vx Id _π 1/2−Bridge Id Vs 2Vs ω Lc ω Lc −

Power Factor and Measures of

Distortion

Read Chapter 3 of “Principles of Power Electronics” (KSV) by J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Addison-Wesley, 1991. Look at the AC side.

Definitions and Identities

Two functions X and Y are orthogonal over [a, b] if:

Z b

X(t)Y (t)dt = 0 (3.1)

a

Now:

R 2π

sin(mωt) sin(nωt + φ)dωt = 0, if n = m sinusoids of different frequencies 0

• 6 ⇒

are orthogonal.

17

R 2π

• 0 sin(ωt) cos(ωt)dωt = 0 ⇒ sine and cosine are orthogonal. In general:

1 Z 2π 1

sin(ωt) sin(ωt + φ) = cos φ (3.2)

2π 0 2

These definitions will be useful for calculating power, etc. Suppose we plug a resistor into the wall.

Rwire _Fuse i + V RL VsSin(ωt) − Figure 3.1: Resistor P = < V i > = VRM S iRM S = i2 _{R (3.3)} RM S

The fuse is rated for a specific RMS current. Above that, it will blow so that dissipation in Rwire does not start a fire. Neglecting Rwire, for 115VAC,RM S , 15ARM S fuse, we get ∼ 1.7kW max from wall.

Suppose instead we plug an inductor into the wall. Neglecting Rwire:

Z Z s Z Rwire _Fuse i + V L VsSin(ωt) − Figure 3.2: Inductor Vs i = − ωL cos(ωt) (3.4) 1 < P > = V (t)i(t)d(ωt) 2π V 2 = ₋ s sin(ωt) cos(ωt)d(ωt) 2πωL = 0 (of course) (3.5)

Mathematically, it is because V and i are orthogonal. While we draw no real power, we still draw current.

1 2π iRM S = i2(ωt)d(ωt) 2π 0 Vs = _√ (3.6) 2ωL @115V, 60Hz, L ≤ 20mH → iRM S ≥ 15A (3.7)

X

s

Z

19

draw any real power at the output! (some power dissipated in Rwire). In this case we are not utilizing the source well.

Power Factor

To provide a measure of the utilization of the source we define Power Factor.

. < P > Real Power

P.F. = = (3.8)

VRM S iRM S Apparent Power

For a resistor < P >= VRM S iRM S → P.F. = 1 best utilization. For a inductor < P >= 0 _→ P.F. = 0 worst utilization.

Consider a rectifier drawing some current waveform,

VsSin( t)ω V(t)

+ Rectifier

i(t)

−

Figure 3.3: Rectifier

Express i(t) as a Fourier series:

∞

i(t) = in sin(nωt + φn) Sum of weighted shifted sinusoids (3.9) n=0 1 1 1 Note: iRM S = i12 + i22 + + i2 + 2 2 · · · 2 n · · · 1 < P > = V (t)i(t)d(ωt) 2π 2π

Z Z Z 1 X = Vs sin(ωt) in sin(nωt + φn) 2π 2π _n ∞ X 1 = Vsin sin(ωt) sin(nωt + φn) (3.10) 2 2π n=0

By orthogonality all terms except fundamental drop out.

1 < P > = Vsi1 sin(ωt) sin(ωt + φ1) 2 2π Vsi1 = cos φ1 2 = Vs,RM S i1,RM S cos φ1 (3.11)

So the only current that contributes to real power is the fundamental component in phase with the voltage.

VRM S i1,RM S P.F. = cos φ1 VRM S iRM S i1,RM S = cos φ1 (3.12) iRM S We can break down into two factors:

i1,RM S

P.F. = ( ) cos φ1

iRM S ·

= kd(distortion factor) k· θ(displacement factor)

(3.13) • kd, distortion factor (≤ 1) tells us how much the utilization of the source is

v u v u P v u t s u P 21

• kθ, displacement factor (≤ 1) tells us how much utilization is reduced due to phase shift between the voltage and fundamental current.

Total Harmonic Distortion (THD)

Consider another measure of distortion: Total Harmonic Distortion (THD).

. n=1 in 2

T HD = t 6 (3.14)

i2 1

This measure the RMS of the harmonics normalized to the RMS of the funda­ mental (square root of the power ratio). Distortion factor and THD are related:

u _n=1 i2 T HD = t 6 n i2 1 u i 2 RM S − i 2 1,RM S = i2 1,RM S i2 T HD2 ₌ i2 RM S − 1 1,RM S i2 RM S _{= 1 + T HD}2 i2 1,RM S iRM S = √1 + T HD2 i1,RM S 1 kd = (3.15) 1 + T HD2 Example: V = Vs sin(ωt)

³ ´ 



 4 ipk

 in = _{πn 2}

i(t) = square wave

   i₀ = i_ave = 1 2 ipk T HD = 121% ipk 4 1 2 · π · √2 kd = _ipk √ 2 2 = π P.F. = 0.63 (3.16) i(t) Ipk ω t π 2π Figure 3.4: Example

(Passive) Power Factor Compensation (KSV: Section 3.4.1)

Lets focus on the displacement factor component of power factor. For simplicity, lets assume a linear load (e.g. R-L) so that voltages and currents are sinusoidal.

For sinusoidal V and i:

< P >

P.F. = = cos φ (3.17)

VRM S iRM S φ is the power factor angle:

Leading φ < 0 Capacitive •

Lagging φ > 0 Inductive •

23

Real power:

P = VRM S IRM S cos φ (3.18)

Define reactive power as:

.

Q = VRM S IRM S sin φ (3.19)

Q

S

P

Figure 3.5: Reactive Power

In vector form S~ = P + jQ. In phaser form V ,~ ~i _→ S~ =< V I∗ _>

units

Apparent Power S =_{k S~ k= V}RM S IRM S V A

Average Power Re_{{S} = P = V}RM SIRM S cos φ W Reactive Power Im_{{S} = Q = V}RM S IRM S sin φ V AR

We can use these results to help adjust the displacement factor of a system. (make Qnet → 0).

i θ 2 2 R +(ω L) ω L L VsCos(ω t) _R Im _S i* R _{v Re} i Figure 3.6: R-L Load

Suppose we have an R-L load (e.g. an induction machine):

Vs ωL

i(t) = √

ω2_L2 _{+ R}2 cos(ωt − arctan( _R )) since S = . V I∗

ωL

voltage-current phase φ = arctan( )

R ωL P.F. = cos(arctan( )) R R = √ R2 _{+ ω}2_L2 < 1 (3.20)

We can add some additional reactive load to balance out and give net unity power factor. S = VRM S IRM S = V 2 2√ω2_L s 2 _{+ R}2 (3.21) P = S cos φ = VRM S IRM S cos φ

25 V 2 R = s (3.22) 2(ω2_L2 _{+ R}2₎ jQ = jS sin φ = jVRM S IRM S sin φ ωLV 2 = j s (3.23) 2(ω2_L2 _{+ R}2₎ So we have real and reactive power.

Suppose we add a capacitor in parallel: i’ C VsSin(ωt) Figure 3.7: Capacitor Zc 1 Zc Vphase − iphase i′ S′ P ′ 1 = jωC = 1 e−j π ₂ ωC = ωCej π 2 (3.24) = −90◦ π = VsωC sin(ωt + ) (3.25) 2 = VRM S IRM S 1 = V s 2 ωC (3.26) 2 = 0 (3.27)

1 Q′ _{= −j}

2 V s 2

ωC (3.28)

So by placing the capacitor in parallel:

t) VsCos(ω L R P, Q Q’ C

Figure 3.8: Parallel Capacitor

S = P + jQ + jQ′

make jQ and jQ′ cancel: Q + Q′ = 0

ωLV 2 ₁ s j 2(ω2_L2 _{+ R}2₎ − j ₂ V 2 ωC = 0 s L C = (3.29) ω2_L2 _{+ R}2 Example: ω = 377RAD/sec (ωHZ) R = 1Ω L = 2.7mH C = 1.32mF ⇒

27

If we know our load, we can add reactive elements to compensate so that no dis­ placement factor reduction of line utilization occurs. Real, reactive power definitions are useful to help us do this. This does not help with distortion factor.

Phase-controlled Rectifiers

Read Chapter 5 of "Principles of Power Electronics" (KSV) by J . G . Kassakian, M. F. Schlecht, and G. C . Verghese, Addison-Wesley, 1991.

Thyristor Devices: SCR (Silicon Controlled Rectifier)

K

Figure 4.1: Thyristor

SCR: Acts like a diode where you can select when conduction will start, but not when it stops.

Once on, behaves like a diode and does not t u r n off until i +0.

To stay off (after VaK

>

0 again) must have i stay a t 0 for a short time

t,

(10

-loops)

So the device is semi-controlled: we control the turn on point, but only turns off when circuit conditions force it to.

Simple example:

Figure 4.2: Example

Phase of thyristor turn on (with respect t o line voltage) is termed firing angle a . Consider a full-bridge converter (inductive/current load).

A o t 2-Dl, D2

_./

D3, D4 / - Conduct

- -

Conduct

Figure 4.3: Diode Version

Thyristor (phase-cont rolled) version (firing angle a ):

Ql,Q2 == Q3,Q4 Con uct ( Conduct Conduct

Figure 4.4: Thyristor Version

Id >0 by necessity (conducbon of thyristor) A <Vx> Rectification a

z

>

Rectification Inversion ( < v x > > o \/

- -

< v x > < o >

Power Flows Power Flows ...

AC -> DC DC -> AC

Quadrants of 0ration

in ol,17

Figure 4.5: Output Voltage

So with a phase controlled converter, we can regulate the output voltage by varying firing angle a . We can even cause power flow from dc-side to ac-side as long as Id

>

0

(e.g., pull power out of inductor and put into line).

Consider the power factor of a phase-controlled converter: V,i

Phase shift of fundamental of square wave in phase with square wave, therefore,

= a . So the power factor of a phase-controlled converter varies with firing angle

a .

Consider the effect of ac-side reactance:

No LC + r Ql r

Q ~ A

LC

-

il A 4 4 il VsSin@t) Qz r -+ ~ d No LC

\

a+u o t > a n -Id QLQZ Q3,Q4 All- All-+?-= e +?-= e + e Q3,Q4

Figure 4.7: AC-S ide Reactance

Similar t o the diode rectifier case, a commutation period exists during which all

devices are on, while current in

LC

switches between

+Id

and

-Id

(between Q1/Q2

A

similar analyze t o t h e diode case shows t h a t for t h e full-bridge thyristor con- verter:

2K

<

v,

>=

-[cos a -

-1

X c I d

K

n-Note t h a t t h e need t o commutate devices places a limit on how negative t h e output

voltage can be made as a function of X$-d and a . This is analyzed in KSV, Chapter

5. (require a

+

u

<

n-) . Summary: VdO

!

Commutation Limit Figure 4.8: Summary

X

Introduction to DC/DC

Converters

Analysis techniques: Average KVL, KCL, P.S.S. Conditions.

KCL I1 i2 in Figure 5.1: KCL ij = 0 (5.1) 34

Z X Z Z X 35

Average over time:

1 X ij = 0 T T X 1 Z T T ij = 0 X < ij > = 0 (5.2)

KCL applies to average current as well as instantaneous currents. (Derives from conservation of charge). KVL V2 Vn V1 + − + − + − Figure 5.2: KVL Vk = 0 (5.3)

Average over time:

1 X Vk = 0 T T X 1 Vk = 0 T T < Vk > = 0 (5.4)

X

X

KVL applies to averaged variables.

P.S.S.

To analyze converters in Periodic Steady State (P.S.S.):

Average KCL < ij > = 0 (5.5) Average KVL < Vk > = 0 (5.6) diL from < VL > = L < > dt diL in P.S.S. < > = 0 dt Inductor in P.S.S. < VL > = 0 (5.7) dVL from < iC > = C < > dt dVL in P.S.S. < > = 0 dt Capacitor in P.S.S. < iC > = 0 (5.8)

If Circuit is Lossless: Pin = Pout (5.9)

Consider the DC/DC converter from before (see Figure 5.3):

q(t) iL

I2 ₁ Pulse Width Modulation (PWM) + − I1 _{q(t) = 1} + _t + q(t) = 0 + VL − dT T T+dT 2T Duty Ratio d Vx C2 V2 Vx(t) V1 C1 V1 − (V1>0) _{<Vx> = dV1} − t dT T T+dT 2T Figure 5.3: DC/DC Converter

37

Assume L’s and C’s are very big, therefore:

vC (t) ≃ VC (5.10)

iL(t) ≃ IL (5.11)

Analyze (using average relations) in P.S.S.: < VL > = 0 < VL > = dT (V1 − V2) + (1 − d)T (−V2) dV1T − V2T = 0 V2 = dV1 (5.12) (Since < VL >= 0, < V2 >=< Vx >= dV1.) Consider currents: < iC2 > = 0 I1 = I2 (5.13) < iC1 > = 0 IC1 = (I1 − I2dT ) + I1(1 − d)T = 0 I1 = dI2 (5.14) Combining: I1 = dI2 dV1 = V2 dV1I1 = dI2V2 V1I1 = I2V2 (5.15)

Therefore, power is (ideally) conserved.

Note: Trick in this type of “average” analysis is to be careful when one can use an average value and when one must consider instantaneous quantities.

With the following type of external network and V1, V2 > 0, power flows from 1 _→ 2.

Switch implementation: “buck” or “down” converter (see Figure 5.4).

+ V1 C2 + V2 C1 − −

Figure 5.4: Buck (down) Converter

Type of “direct” converter because a DC path exists between input and output in one switch state.

Suppose we change the location of source and load: Refine switching function so q(t) = 1 when switch is in down position (see Figure 5.5).

Similar analysis: < VL > = 0 (V1 − V2)(1 − d)T + V1dT = 0 1 V2 = V1 (5.16) 1 − d By conservation of power: I2 = (1 − d)I1 (5.17)

39 q(t) 1 iL t I2 I1 _{q(t) = 0 dT T T+dT 2T} + -+ Vx(t) - + + _{q(t) = 1} VL V2 V2 C1 Vx C2 V1 t - _{dT T T+dT 2T} -VL dT T V1 V1-V2

Figure 5.5: Change the Location of Source and Load

In this case, energy flows from 2 ← 1 and the P.S.S. output voltage (V2) is higher than input voltage (V1).

With the following switch implementation: “boost” or “up” converter. Another type of “direct” converter (see Figure 5.6).

C2 C1 V2 + + V1 − −

Figure 5.6: Boost (up) Converter

In general power flows direction depends on:

1. External network 2. Switch implementation

3. Control

We may need to know all of these to determine behavior.

The boost converter is often drawn with power flowing left to right. However, there is nothing fundamental about this (see Figure 5.7).

C1 C2 + V1 V2 + − −

Figure 5.7: Boost (up) Converter Drawn Left to Right

Boost: Switch turns on and incrementally stores energy from V1 in L. Switch truns off and this energy and additional energy from input is transferred to output. Therefore, L used as a temporary storage element.

Either the buck or boost can be seen as the appropriate connection of a canonical cell (see Figure 5.8).

A

B

C

Figure 5.8: Direct Canonical Cell

The “direct” connection has B as the common node. The rest of operation is determined by external network, switch implementation and control.

Switch implementation: Different switches can carry current and block voltage only in certain directions.

41

MOSFET can block positive V and can carry positive or negative i (see Figure 5.9).

D D i + G V − Body Diode G S S Figure 5.9: MOSFET

BJT (or darlington) is similar, but negative V blows up device (see Figure 5.10).

i i + _{Same for} + V V − IGBT − Figure 5.10: BJT Combine elements:

1. Block positive V and carry positive and negative i (see Figure 5.11).

+ V i

−

Figure 5.11: Combine Elements 1

i +

V

−

Figure 5.12: Combine Elements 2

3. Block positive and negative V and carry positive and negative i (see Fig­ ure 5.13).

i +

V

−

Figure 5.13: Combine Elements 3

We can also construct indirect DC/DC converters. Store energy from input, trans­ fer energy to output, never a DC path from input to output (see Figure 5.14).

+ + B A V1 V2 − − C

Figure 5.14: Canonical Cell Split capacitor (see Figure 5.15):

43 q(t) = 1 q(t) = 0 + − q(t) + V1 _{V2 1} t − dT T T+dT 2T q(t) = 0 q(t) = 1 V2 V1 VL T dT C2 + V2 − − C1 V1 + Split Capacitor

Figure 5.15: Indirect DC/DC Converter < VL > = 0 < VL > = V1dT + (1 − d)T V2 d V2 = − V1 (5.18) 1 − d V2 f or 0 < d < 1 → −∞ < < 0 (5.19) V1 • Store energy in L(dT ) from V1.

• Discharge it (the other way) in V2. (must have voltage inversion).

V1 + + V2 I2 I1 − −

Figure 5.16: “Buck/Boost” or “up/down” converter

V1 > 0 I1 > 0 V2 < 0 I2 > 0

Other indirect converters include CUK and SEPIC variants.

Given conversion range _{−∞ <} V2 _{< 0, why not always use indirect vs. direct?}

V1

1. Sign inversion (can fix)

2. Device and component stresses

Look at averaged circuit variables (see Figure 5.17): Assume C, L are very large. IL = I1 + I2

|IL| = |I1| + |I2| (5.20)

By averaged KCL into dotted box: Maybe counter intuitive: I1 = average tran­ sistor current. I1 + I2 = peak transistor current.

45 V1 + + V2 I2 I1 + IL iq VC − − − iq I1+I2 I1 dT T

Figure 5.17: Averaged Circuit Variables By averaged KVL around loop:

VC = V1 − V2

|VC | = |V1| + |V2| (5.21)

Therefore, for big L, C (see Figure 5.18):

V1 + + V2 I2 I1 Q D V1−V2 I1+I2 − − − + Figure 5.18: Big L, C Indirect converter:

So Q, D, L see peak current I = I1 + I2, Q, D, C block peak voltage V = V| | | |1 + V2 . Consider direct converters (see Figure 5.19):

+ I1 Boost D Q Vq Buck + Vq + I2 Vd Q D C V2 + V1 + + − V1 + ₋ − − − − − C V2

Figure 5.19: Direct Converters Buck: VC = Vq,max = Vd,max = V1 (5.22) IL = iq,max = id,max = I2 (5.23) Boost: VC = Vq,max = Vd,max = V2 (5.24) IL = iq,max = id,max = I1 (5.25)

Direct converters (either type):

VC = Vq,max = Vd,max = max(V1, V2) (5.26)

IL = iq,max = id,max = max(I1, I2) (5.27)

Device voltage and current stresses are higher for indirect converters than for direct converters with same power. Inductor current and capacitor voltage are also higher.

Summary:

47 VC + − V1 + + V2 I2 I1 iL − − iq I1+I2 I1 dT T

Figure 5.20: Indirect Converters (neglecting ripple)

IL = isw,pk = id,pk = I| | | | 1 + I2 (5.28)

VC = Vsw,pk = Vd,pk = V| | | | 1 + V2 (5.29)

For direct converters (neglecting ripple) (see Figure 5.21):

IL + Boost Vq + V2 IL Buck + Vq + Vd V2 + V1 + − V1 + − − − − − −

Figure 5.21: Direct Converters (neglecting ripple)

IL = isw,pk = id,pk = max(I1, I2) (5.30)

VC = Vsw,pk = Vd,pk = max(V1, V2) (5.31)

Based on device stresses we would not choose an indirect converter unless we needed to, since direct converters have lower stress.

5.1 Ripple Components and Filter Sizing

Now, selecting filter component sizes does depend on ripple, which we have previously neglected. Lets see how to approximately calculate ripple components. To eliminate 2nd order effects on capacitor voltage ripple:

1. Assume inductor is ∞(Δipp → 0).

2. Assume all ripple current goes into capacitor.

Similarly, to eliminate 2nd order effects in inductor current ripple: 1. Assume capacitors are ∞(ΔVC,pp → 0).

2. Assume all ripple voltage is across the inductor. We can verify assumptions afterwards.

Example: Boost Converter Ripple (see Figure 5.22)

+ V2 id id I1 V1 + ₋ − − + V2

Figure 5.22: Boost Converter Ripple Find capacitor (output) voltage ripple (see Figure 5.23): Assume L _{→ ∞, therefore, i}1(t) → I1.

~

49 5.1. RIPPLE COMPONENTS AND FILTER SIZING

Figure 5.23: Capacitor Voltage Ripple id Including Ripple D Actual Waveform i Id=<id>=(1-D)I1 T I1 id t DT DI1 t DT T C R −(1−D)I1 + ~ ~ _~ id V _VC − ΔVCpp 2 t T − ΔVCpp 2 DT

Figure 5.24: Ripple Model with Capacitor If we assume all ripple current into capacitor 1

2πfsw C ≪ R or ˜V2 is small recpect

to V2.

Let us calculate the ripple:

i = C dVC dt ΔVC,pp = Z DT 0 1 − D C I1dt = (1 − D)DT C I1 (5.32)

~

Z

(1 − D)DT

C ≥ I1 (5.33)

ΔVC,pp

Now let us find the capacitor voltage ripple (see Figure 5.25):

<Vx>=(1−D)V2 T V2 Vx + Vx Source Impedance Zi V1 + + V2 C1

Actual Vx Including Ripple

t DT − − − Figure 5.25: Ripple

Replace Vx with equivalent source and eliminate DC quantities (see Figure 5.26).

Vx DV2 t DT T −(1−D)V2 + ~ ~ _~ i1 Vx _i1 − Δ ipp 2 t T − Δ ipp 2 DT

Figure 5.26: Ripple Model with Inductor Neglecting the drop on any source impedance (|Zi| ≪ 2πfswL).

1 DT ΔiL,pp = (1 − D)V2dt L 0 D(1 − D)T = V2 (5.34) L

51 5.1. RIPPLE COMPONENTS AND FILTER SIZING

Therefore, we need:

L ≥ D(1 _Δ− _i pp

D)T

V2 (5.35)

Energy storage is one metric for sizing L’s and C’s. Physical size may actually be determined by one or more of: energy storage, losses, packing constraints, material properties. To determine peak energy storage requirements we must consider the ripple in the waveforms.

Define ripple ratios (see Figure 5.27):

ΔVC,pp RC = 2VC (5.36) ΔiL,pp RL = 2I − L (5.37)

This is essentially % ripple: peak ripple magnitude normalized to DC value.

X Xpk − Xpp 2 Δ Xpp 2 Δ

Figure 5.27: Ripple Ratios

Specification of allowed ripple and converter operating parameters determines capacitor and inductor size requirements.

Therefore:

VC,pk = VC (1 + RC ) (5.38)

So from our previous results (boost converter): (1 − D)DT _I 1 (5.40) C ≥ 2RC VC D(1 − D)T_V 2 (5.41) L ≥ 2RLI1

The ripple ratios also determine passive component energy storage requirements and semiconductor device stresses.

So lets calculate the required energy storage for the capacitor: 1 CV 2 EC = 2 C,pk 1 (1 − D)DT _I 1V 2 = 2 2RC VC (1 + R C )2 C DI2V2 (1 + RC )2 = 4fsw RC DPo (1 + RC )2 = (5.42) 4fsw RC

So required capacitor energy storage increases with: 1. Conversion ratio

2. Power level

and decreases with switching frequency. Similar result for inductor energy storage:

(1 − D)Po (1 + RL)2

EL = (5.43)

4fsw RL

It can be shown that direct converters always require lower energy storage than indirect converters.

53 5.2. DISCONTINUOUS CONDUCTION MODE

Table 5.1: Effect of Allowed Ripple on Switches

Converter Type Value L, C _{→ ∞} Finite L, C

Direct Indirect isw,pk, id,pk Vsw,pk, Vd,pk isw,pk, id,pk Vsw,pk, Vd,pk max_{(|I1|, |I2|)} max_{(|V1|, |V2|)} |I1|, |I2| |V1|, |V2| max_{(|I1|, |I2|)(1 + R}L) max_{(|V1|, |V2|)(1 + R}C ) (|I1|, |I2|)(1 + RL) (|V1|, |V2|)(1 + RC )

Consider effect of allowed ripple on switches (see Table 5.1): Define a metric for switch sizing (qualitative only):

.

Switch Stress P arameter(SSP ) = Vsw,pkisw,pk (5.44)

For a boost converter:

SSP = max(V1, V2)(1 + RC )max(I1, I2)(1 + RL) = V2(1 + RC )I1(1 + RL) Po = (1 + _RC )(1 + RL) 1 − D V2 = Po (1 + RC )(1 + RL) (5.45) V1 Therefore, SSP gets worse for: • Large power

• Large conversion ratio • Large ripple

5.2 Discontinuous Conduction Mode

Consider the waveform of the boost converter (see Figure 5.28):

q(t)

Switching Function for Diode qD(t) t I1 DT T VL L _{R +} + − C q(t) _V2 V1 − _V1−V2 iL T DT t V1 I1 t DT T

Figure 5.28: Boost Converter Waveforms V1DT ΔiL,pp = (5.46) L IL = I1 V2 = (5.47) R(1 − D) ΔiL,pp 2 RL = I1 V1D(1 − D)RT = 2V2L D(1 − D)2 RT = (5.48) 2L RL ↑ as R ↑, L ↓ (5.49)

(see Figure 5.29 for an illustration)

Eventually peak ripple becomes greater than DC current: both switch and diode off for part of cycle. This is known as Discontinuous Condition Mode (DCM). It

55 5.2. DISCONTINUOUS CONDUCTION MODE

t iL As R Increases t iL DT T DT T As L Decreases

Figure 5.29: Changing R and L happens when RL > 1. D(1 − D)2 RT RL = 2L RL R > ≥ 1 2L (5.50) D(1 − D)2_T

At light load (big R and low power) we get DCM. Lighter load can be reached in CCM for larger L. DCM occurs for:

L ≤ D(1 − D)

2 T R

(5.51) 2

The minimum inductance for CCM operation is sometimes called the “critical inductance”.

D(1 − D)2 T R

LCRIT,BOOST = (5.52)

2

For some cases (e.g. we need to operate down to almost no load), this may be unreasonably large.

Because of the new switch state, operating conditions are different (see Fig­ ure 5.30).

q(t), q D(t) VL DT t DCM (D+D2)T T V1 (D+D2)T t DT _T V1-V2

iL Must Be Zero in Remaining Time

t DT (D+D2)T T

Figure 5.30: Different Operating Conditions Voltage conversion ratio:

< VL > = 0 in P.S.S. V1DT + (V1 − V2)D2T = 0 V1(D + D2) = V2D2 V2 D + D2 = V1 D2 D = 1 + (5.53) D2 where D2 < 1 − D.

How does this compare to CCM? In CCM:

V2 1

=

s

57 5.2. DISCONTINUOUS CONDUCTION MODE

1 − D + D = 1 − D D = 1 + (5.54) 1 − D Since V_{2 = 1 +} D _{and D} 2 < 1 − D, V2 is bigger in DCM. V1 D2 V1

Eliminating D2 from equations, can be shown for boost:

V2 1 1 2D2RT

= + 1 + (5.55)

V1 2 2 L

Therefore, conversion ratio depends on R, fsw, L, ... unlike CCM. This makes control tricky, as all of our characteristics change for part of the load range.

How do we model DCM operation? Consider diode current (see Figure 5.31).

IL id id ipk + − + + V2 id(t) V2 V1 − − I2 t DT (D+D2)T T

Figure 5.31: DCM Operation Model

V1DT ipk =

L

Δi = L V V1DT = L L V2 − V1 V1D D2 = (5.56) V2 − V1 < iout > = < id > 1 1 = (D2T )(ipk) 2 T 1 V1 V1DT 1 = ( DT )( ) 2 V2 − V1 L T V 2_{T D}2 = 1 (5.57) 2(V2 − V1)

Model as controlled current source as a function of D.

So DCM sometimes occurs under light load, as dictated by sizing of L. • Sometimes we can not practically make L big enough.

• Must handle control (changes from CCM to DCM).

• Also, we get parasitic ringing in both switches (see Figure 5.32). Vx

+ −

Ideal _{L Rings with Parasitic C’s} V2 + + V2 V1 Vx V1 − ₋ t DT D2T T

Figure 5.32: Parasitic Ringing

Sometimes people design to always be in DCM. Inductor size becomes very small and we can get fast di _{(see Figure 5.33).}

59 5.2. DISCONTINUOUS CONDUCTION MODE

CCM _DCM

Desired i

V2

di/dt limited so cannot respond fast.

Figure 5.33: Design in DCM In this case we get:

1. Very fast di _capability. dt

2. Simple control model iout = f (D).

3. Small inductor size (EL minimized @ RL = 1) But we must live with:

1. Parasitic ringing

2. High peak and RMS currents 3. Need additional filters

DCM is sometimes used when very fast response speed is needed (e.g. for voltage regulator modules in microprocessors), especially if means are available to cancel ripple (e.g. interleaving of multiple converters). In many other circumstances DCM is avoided, though one may have to operate in DCM under light-load conditions to keep component sizes acceptable.