Chapter 10. Boundary Scan and Core-Based Testing

(1)

Chapter 10

Boundary Scan and

Core

(2)

Outline

Introduction

Digital Boundary Scan (1149.1)

Boundary Scan for Advanced Networks

(1149.6)

Embedded Core Test Standard (1500)

Comparison between 1149.1 and 1500

(3)

Boundary Scan

Original objective: board-level digital testing

Now also apply to:

MCM and FPGA

Analog circuits and high-speed networks

Verification, debugging, clock control, power

management, chip reconfiguration, etc.

(4)

Boundary Scan Family

Std. 1149.5-1995

(not endorsed by

IEEE since 2003)

Standard module test and

maintenance (MTM) bus

1149.5

Std. 1149.4-1999

Mixed-signal test bus

1149.4

Discontinue

Direct access testability interface

1149.3

Discontinue

Extended digital serial interface

1149.2

Std. 1149.1-2001

Digital chips and interconnects

among chips

1149.1

Status

Main target

(5)

Core

-

Based SOC Design

ADC

DAC PLL

RAM RAM

ROM

DSP

BUS & INTERCONNECT

CPU

ASIC 1 ASIC 2

GLUE LOGIC

IP 1

IP 2

(6)

Digital Boundary Scan

–

1149.1

Basic concepts

Overall test architecture & operations

Hardware components

Instruction register & instruction set

Boundary scan description language

On-chip test support

(7)

Basic Idea of Boundary Scan

Internal

Logic

(8)

A Board Containing 4 IC

’

s with

Boundary Scan

Internal Logic Internal Logic Internal Logic Internal Logic

Boundary-scan cell Boundary-scan chain Serial

Data in

Serial Data out

(9)

1149.1 Boundary

-

Scan Architecture

Internal

Logic

Internal Registers Bypass Register Miscellaneous Register 1 Boundary-Scan Register (consists of boundary Scan cells)

(10)

Hardware Components of 1149.1

A test access port (TAP) consisting of :

4 mandatory pins: Test data in (TDI), Test data out (TDO),

Test mode select (TMS), Test clock (TCK), and

1 optional pin: Test reset (TRST)

A test access port controller (TAPC)

An instruction register (IR)

Several test data registers

A boundary scan register (BSR) consisting of boundary

scan cells (BSCs)

A bypass register (BR)

(11)

design-Basic Operations

Basic Operations

1. Instruction sent (serially) through TDI into

instruction register.

2. Selected test circuitry configured to respond to

the instruction.

3. Test pattern shifted into selected data register

and applied to logic to be tested

(12)

Boundary

-

Scan Circuitry in A Chip

TDO

TDI

TRST*

TMS

TCK

Design-Spec. Reg.

Device-ID Reg.

Boundary Scan Reg.

Bypass Reg. (1-bit)

IR decode

Data Register

M

U

X

M

U

X

0

1

1D

EN

T

A

P

ClockDR, ShiftDR, UpdateDR 3

Reset* ClockIR, ShiftIR, UpdateIR

3

T

A

P

C

(13)

Data registers

Boundary scan register: consists of boundary

scan cells

Bypass register: a one-bit register used to pass

test signal from a chip when it is not involved in

current test operation

Device-ID register: for the loading of product

information (manufacturer, part number, version

number, etc.)

(14)

A Typical Boundary

-

Scan Cell (BSC)

Operation modes

Normal: IN

→

OUT (Mode = 0)

Shift: TDI

→

...

→

IN

→

OUT

→

...

→

TDO (ShiftDR = 1, ClockDR)

(15)

TAP Controller

A finite state machine with

16 states

Input: TCK, TMS

Output:

9 or 10 signals

included ClockDR,

UpdateDR, ShiftDR, ClockIR, UpdateIR,

ShiftIR, Select, Enable, TCK and TRST*

(optional).

(16)

State Diagram of TAP Controller

(17)

Main functions of TAP controller

Providing control signals to

Reset BS circuitry

Load instructions into instruction register

Perform test capture operation

Perform test update operation

Shift test data in and out

(18)

States of TAP Controller

Test-Logic-Reset: normal mode

Run-Test/Idle: wait for internal test such as BIST

Select-DR-Scan: initiate a data-scan sequence

Capture-DR: load test data in parallel

Shift-DR: load test data in series

Exit1-DR: finish phase-1 shifting of data

Pause-DR: temporarily hold the scan operation (e.g.,

allow the bus master to reload data)

(19)

Instruction Set

BYPASS

Bypass data through a chip

SAMPLE

Sample (capture) test data into BSR

PRELOAD

Shift-in test data and update BSR

(20)

Execution of BYPASS Instruction

(21)

Execution of SAMPLE Instruction

(22)

Execution of PRELOAD Instruction

R1

R2

R1

R2

Internal

Logic

TDI

TDO

Output

Input

PRELOAD

M

U

X

M

U

X

(23)

Execution of EXTEST Instruction (1/3)

Shift-DR (Chip1)

Internal Logic Registers TDI TDO Internal Logic Registers TDI TDO

(24)

Update-DR (Chip1)

Capture-DR (Chip2)

(25)

Shift-DR (Chip2)

Internal Logic Registers TDI TDO Internal Logic Registers TDI TDO

(26)

Shift-DR

Execution of INTEST Instruction (1/4)

(27)

Update-DR

(28)

Capture-DR

Internal

Logic

Registers

TAP controller

TDI

TDO

(29)

Shift-DR

Internal

Logic

Registers

TDI

TDO

(30)

Boundary Scan Description

Language (BSDL)

Now a part of IEEE 1149.1-2001

Purposes:

Provide standard description language for BS devices.

Simplify design work for BS – automated synthesis is possible.

Promote consistency throughout ASIC designers, device

manufacturers, foundries, test developers and ATE

manufacturers.

Make it easy to incorporation BS into software tools for test

(31)

Features of BSDL

Describes the testability features of BS

devices that are compatible with 1149.1.

S subset of VHDL.

System-logic and the 1149.1 elements that

are absolutely mandatory need not be

specified.

(32)

Scan and BIST Support with

Boundary Scan

(33)

Ring architecture with shared TMS

TDI TCK TMS TDO #1 TDI TCK TMS TDO #2 TDI TDO Bus master Application chips

Bus Master for Chips with

Boundary Scan (1/5)

(34)

Ring architecture with separate TMS

TDI TCK TMS TDO #1 TDI TCK TMS TDO #2 Bus master Application chips TDI TDO TMS1 TMS2 TMSN TCK

Boundary Scan (2/5)

(35)

Star architecture

Boundary Scan (3/5)

(36)

Multi-drop architecture

Bus master Multi-Drop Device Multi-Drop Device Multi-Drop Device

Boundary Scan (4/5)

(37)

Hierarchical architecture

Boundary Scan (5/5)

(38)

Boundary scan for advanced networks

–

1149.6

Rationale

Analog test receiver

Digital driver logic

Digital receiver logic

(39)

Rationale

Advanced signaling techniques are required

for multiple-mega-per-second I/O.

Differential or AC-coupling networks

Coupling capacitor in AC-coupled networks

blocks DC signals.

(40)

Capturing AC

-

Coupled Signal with 1149.1

C U TX RX C U V_T

TX

RX

Update-DR

V

_H

V

_L

V

_H

(41)

1149.1 Configuration for Differential

Signaling

C U

TX RX

(42)

Analog Test Receiver Response to AC

and DC

(43)

Digital Driver Logic

0 1 0 1 _C _U ShiftDR Shift in ClockDR UpdateDR Mode Shift out Data Mission 0 1 AC Mode Train/Pulse

Mode AC Mode Train/Pulse 1149.1 Bypass

1149.1 Extest

0 X X

1 0 X

AC Test Signal Insertion, per driver

(44)

Digital Receiver Logic

VHyst VHyst Pad RF CF VT DC AC EXTEST_PULSE or EXTEST_TRAIN Selected Hyst Mem Clear Set Shift In Capture FF Update FF ClockDR 0 1 ShiftDR Shift Out UpdateDR 0 1 Optional, Required for Observe-and-Control Capabilty on Single-Ended Inputs Only

Boundary Register Cell Test Receiver D EXTEST_PULSE, EXTEST_TRAIN: Init_Memory Latch Q TCK Capture-DR Shift_DR TAP State TMS TCK EXTEST: Init_Memory TAP State Clock_DR Exit*-DR Update_DR

May be located near TAP controller

Capture-DR EXTEST

(45)

Example of Modification on 1149.1 TAP

–

Driver Behavior During EXTEST_PULSE

TCK

(TAP State)

Test-Logic Reset Select-DR Capture-DR

AC Test Signal

Pulse Width

(46)

Embedded Core Test Standard

-

1500

SOC test problems

Overall architecture

Wrapper components and functions

Instruction set

Core test language

Core test supporting and system test

configurations

(47)

Mixing technologies: logic, processor, memory, analog

Need various DFT/BIST/other techniques

Deeply embedded cores

Need Test Access Mechanism

Hierarchical core reuse

Need hierarchical test management

Different core providers and SOC test developers

Need standard for test integration

SOC Test Problems/Requirements (1/2)

(48)

Higher-performance core pins than SOC pins

Need on-chip, at-speed testing

External ATE inefficiency

Need “on-chip ATE”

Long test application time

Need parallel testing or test scheduling

Test power must be considered

Need lower power design or test scheduling

Testable design automation

SOC Test Problems/Requirements (2/2)

(49)

A System Overview of IEEE 1500

Standard

(50)

Test Interface of A Core Wrapper

Core W SC W PI W PO W PC W SI W rapper W SO W rapper Serial Input W rapper Serial Output W rapper Parallel Control W rapper Parallel Input W rapper Parallel Output Optional W rapper Parallel Port (W PP)

(51)

Serial Test Circuitry of 1500 for a Core

(52)

Wrapper Components

Wrapper series port (WSP)

Wrapper series input (WSI), Wrapper series output

(WSO), Wrapper series control (WSC)

Wrapper parallel port (WPP)

(optional)

Wrapper parallel input (WPI), Wrapper parallel output

(WPO), wrapper parallel control (WPC)

Wrapper instruction register (WIR)

Wrapper bypass regiester (WBY)

(53)

Wrapper Series Control (WSC) signals

WRCK: wrapper clock terminal

AUXCK

n

: Optional auxiliary clocks, where

n

is

the number of the clocks.

WRSTN: wrapper reset

SelectWIR: determine whether WIR is selected

CaptureWR: enable Capture operation

(54)

Wrapper Instruction Register

(55)

Wrapper Boundary Register (WBR)

Consists of Wrapper boundary cells (WBC’s)

WBC

Terminals

: Cell functional input (CFI), cell

functional output (CFO), cell test input (CTI), cell

test output (CTO)

(56)

Events of WBR (WBC)

Shift: data advance one-bit forward on WBR’s

shift path

Capture: data on CFI or CFO are captured and

stored in WBC

Update: data stored in WBC’s shift path storage

are loaded into an off-shift-path storage of the

WBC

Transfer: move data to the storage closest to CTI

or one bit closer to CTO

Apply: a derivative event inferred from other

(57)

Four Symbols Used in Bubble Diagrams for

WBC

’

s

Storage

element

Data

path

Decision

point

Data paths

from a source

(58)

Some Typical

WBC

’

s

Represented by

Bubble Diagrams

(59)

Example 10.1

-

WIR Interface of WBY,

WBR

WDR(s

) and

CDR(s

)

W IR C ir cu itr DR_Select[n:0] CDR_Cntrl WDR_Cntrl Core_Cntrl {SelectWIR, WRCK, WRSTN, CaptureWR, ShiftWR, UpdateWR} WBR CDR k DR_Select[n:0] SelectWIR WIR_WSO WSO

(60)

Example 10.2

-

Schematic Diagram of

WBC WC_SD2_CIO

CFO MODE D2 D1 CAPT CFI XFER CTI SHIFT WRCK CTO

(61)

WS_BYPASS Instruction

(62)

WS_EXTEST Instruction

(63)

WP_EXTEXT Instruction

(64)

WS_SAFE Instruction

WSO

Disabled

Core

FO

FI

FO

FI

W

B

R

W

B

R

Safe

States

Safe

States

WSI

WIR

Bypass

(65)

WS_PRELOAD Instruction

(66)

WP_PRELOAD Instruction

(67)

WS_CLAMP Instruction

(68)

WS_INTEST Instruction

(69)

WS_INTEST_SCAN Instruction

(70)

General Parallel TAM Structure

(71)

Multiplexed TAM Architectures

(72)

Daisy chained TAM Architecture

(73)

Direct Access TAM Architectures

(74)

Local Controller TAM Architectures

(75)

Core Access Switch (CAS) Architecture

(76)

Different Functional Modes of CAS

(77)

Various Types of Test Supporting

Using CAS Structure

(78)

A Hierarchical Test Architecture

Supporting Plug & Play Feature

(79)

Detailed I/O and CTC of The

Hierarchical Test Architecture

(80)

A Hierarchical Test Architecture with I/Os

Compatible to 1149.1

(81)

Comparison between 1149.1 and 1500

No

Yes

Latency between

Yes

No

Transfer Mode

Yes

No

Parallel Mode

No

Yes

FSM

Mandatory: WSI, WSO, 6 WSC

Optional: TransferDR, WPP,

AUXCKn(s)

Mandatory: TDI, TDO,

TMS, TCK

Optional: TRST

Extra Data/Control

I/Os

Core-based

Board-level

Purpose

1500

1149.1