Experiment EB1: FET Amplifier Frequency Response

Experiment EB1: FET Amplifier Frequency Response

Learning Outcome

• LO4: Analyze the operation of JFET, MOSFET and BJT amplifiers and switching circuits

1.0Apparatus

Equipment required Components required

Power Supply – 1 N-channel JFET 2N5457 – 1 Oscilloscope – 1 Resistor 10kΩ (1/4W) – 2 Digital Multimeter – 1 Resistor 3.3kΩ (1/4W) – 1

Breadboard – 1 Resistor 3.9kΩ (1/4W) – 1

Function Generator – 1 Resistor 22kΩ (1/4W) – 1 Mylar Capacitor 0.47µF – 2 Mylar Capacitor 0.1µF – 1 Mylar Capacitor 0.01µF – 1 50 kΩ potentiometer -- 1 Objectives:

1. Construct and test a voltage amplifier using N-channel JFET device in a common source configuration

2. Apply the voltage divider biasing method to set the DC operating point (VGSq ,IDSq) .

Verify the estimated DC operating point with the measured data.

3. Investigate the effect of frequency changes on the voltage gain of the amplifier, measure its frequency response and obtain its operating bandwidth.

4. Investigate the capacitance effect on the frequency response of the common source JFET amplifier

Important Notes

All related calculation questions that does not require experimental data must be answered before coming to the lab. You are required to show all the calculation steps when requested by the lab instructor. During the evaluation session, your lab instructor may request you to demonstrate how the measurement data is obtained and explain your experimental results.

Report Submission

2.0Background Theory

An amplifier is a circuit that increases/decrease the input signal value and in this experiment the signal to be amplified is the voltage. In this experiment you are going to investigate frequency response characteristic of a voltage amplifier circuit using the N-channel JFET device

Most amplifiers have relatively constant gain over a certain range of frequencies. This range of frequencies is called the bandwidth of the amplifier. The bandwidth for a given amplifier depends on the circuit component values, the type of active components and the dc operating point of the active component. When an amplifier is operated within its bandwidth, the current gain

( )

A_i , voltage gain

( )

A_v , and power gain

( )

A_p values are referred to as midband gain values. A simplified frequency-response curve that represents the relationship between amplifier gain and operating frequency is shown in Figure 1.

Figure 1: A simplified frequency response curve

As the frequency-response curve shows, the power gain of an amplifier remains relatively constant across a band of frequencies. When the operating frequency starts to go outside this frequency range, the gain begins to drop. Two frequencies of interest, f_c1andf_c2 , are the frequencies at which power gain decreases to approximately 50% ofA_p(mid). The frequencies labeled f_c1 and f_c2 are called the lower and upper cutoff frequencies of an amplifier, respectively. These frequencies are considered to be the bandwidth limits for the amplifier and thus bandwidth BW is given by

1

2 c

c f

f

BW = − .

The geometric average of f_c1 and f_c2 is called the geometric center frequency foof an

amplifier, given by

2 1 0 fc fc

f = .

When the operating frequency is equal to f₀, the power gain of the amplifier is at its maximum value.

Frequency response curves and specification sheets often list gain values that are measured in decibels (dB). The dB power gain of an amplifier is given by

Apdrops at

lowerfrequencies A_frequenciespdrops at higher

fc1 _fc2 Bandwidth 0.5Ap(mid) Ap(mid) Frequency Power Gain Mid-band

in out p dB p P P A A _{( )}=10log =10log .

Positive and negative decibels of equal magnitude represent reciprocal gains and losses. A +3dB gain caused power to double while a –3dB gain caused power to be cut in half.

Using the basic power relationships,

L out out R v P 2 = and in in in R v P 2

= , the power gain may be rewritten as in in L out in out dB p R v R v P P A ₂ 2 ) ( =10log =10log L in in out R R v v log 10 log 20 + =

The voltage component of the equation is referred to as dB voltage gain. When the amplifier input and out resistances are equal

) ( ) ( 20log vdB in out dB p A v v A = = . (R_in =R_L)

Thus, when the voltage gain of an amplifier changes by –3dB, the power gain of the amplifier also changes by –3dB.

Low Frequency Response of FET Amplifier

In the low frequency region of a single stage FET amplifier as shown in Figure 2(a), it is the RC combinations formed by the network capacitors and the network resistive parameters that determine the cutoff frequency. There are three capacitors – two coupling capacitor C_Gand

D

C , and one bypass capacitor,C_S. Let us assume thatC_G, C_D and C_S are arbitrarily large and can be represented by short-circuit. The total resistance in series with C_G is given by

in G

CG R R

R = +

whereR_in =R₁||R₂ is the input impedance of the amplifier circuit. The power supplied by the signal generator isPin =Vgen2 /(RG +Rin). However, the reactance XCG of capacitance CGis not

negligible at very low frequencies. The frequency at which Pin is cut in half is when

in G CG R R

X = + . Thus the lower half-power point for gate circuit occurs at frequency

(

G in

)

G G CG LG C R R C R f + = = π π 2 1 2 1

Figure 2(a): Schematic diagram of a JFET amplifier

R1 _RS R2 RL RD _C D CS CG RG +VDD Vgen D S G Vin

Figure 2(b): JFET amplifier low-frequency ac equivalent circuit

Figure 2(c): Approximate drain circuit of JFET amplifier (assuming the resistance of the JFET drain terminal, rd, is much larger than RD).

WhenC_G and C_S are arbitrarily large and can be represented by short-circuit, the drain circuit of the JFET amplifier is as shown in Figure 2(c). At high frequency where CD can also

be represented by a short-circuit, the output power to load resistor RLisPout VD /RL

2

= . At low

frequencies where the reactance XCD of capacitance CDis not negligible, Pout is cut in half whenX_CD =R_L. Thus the lower half-power point for drain circuit occurs at frequency

D L LD C R f π 2 1 =

At the half-power point, the output voltage reduces to 0.707 times its midband value. The actual lower cutoff frequency is the higher value between fLG (determined by CG) and fLD

(determined by CD).

High Frequency Response of FET Amplifier

The high frequency response of the FET is limited by values of internal capacitance, as shown in Figure 3(a). There is a measurable amount of capacitance between each terminal pair of the FET. These capacitances each have a reactance that decreases as frequency increases. As the reactance of a given terminal capacitance decreases, more and more of the signal at the terminal is bypassed through the capacitance.

R1||R2 _R S RL RD CD CS CG RG Vgen VG D S G Vin RL RD CD gmVgs D S VD

Figure 3(a): JFET amplifier with internal capacitors that affect the high frequency response.

Figure 3(b): FET amplifier high frequency ac equivalent circuit.

The high frequency equivalent circuit for the FET amplifier in Figure 3(a) is shown in Figure 3(b), including all the terminal capacitance values. C_gdis replaced with the Miller equivalent input and output capacitance values given as

(

1

)

) (M = gd v+ in C A C and v v gd M out A A C C _{( )} = +1

Figure 4: Miller equivalent circuit for a feedback capacitor. R1||R2 Cout(M) RG Vgen C_gs Cin(M) Cds CL R_L||R_D R1 R_S R2 RL RD _CD CS CG RG Cgd Cgs Cds Vgen +VDD CL AV Cgd AV Cin(M) G D G D Cout(M)

Note the absence of capacitorsC_G,C_D and C_S in Figure 3(b), which are all assumed to be short circuit at high frequencies. From this figure, the gate and drain circuit capacitance are given by ) (M in gs G C C C′ = + and C′_D =C_out(M) +C_ds +C_L

whereC_L is the input capacitance of the following stage. In general the capacitance C_gs is the largest of the parasitic capacitances, with C_ds the smallest. The high cutoff frequencies for the gate and drain circuits are then given by

G in HG C R f ′ ′ π = 2 1 and D L HD C R f ′ = ' 2 1 π

whereR_in′ =R_G ||R_in and R'_L=R_D ||R_L. At very high frequencies, the effect of C_G′ is to reduce the total impedance of the parallel combination ofR₁,R₂ and C_G′ in Figure 3(b). The result is a reduced level of voltage across the gate-source terminals. Similarly, for the drain circuit, the capacitive reactance of C_D′ will decrease with frequency and consequently reduces the total impedance of the output parallel branches of Figure 3(b). It causes the output voltage to decrease as the reactance becomes smaller.

3.0Procedures

1. Before connecting the circuit of Figure 5, measure the actual resistance of R1, R2, RD, RS

and RL as accurate as possiblewith a digital multimeter (set it to the best resistance range)

and record the measured values.

2. Connect the common source JFET amplifier circuit as shown in Figure 5 using a breadboard (refer to Appendix B). Do not connect the power supply and the function generator to the circuit yet. Keep the connecting wires on the breadboard as short as possible (< 3 cm) to reduce unwanted inductance and capacitance in your circuit. 3. Set the power supply output to +12V. Connect its output to the circuit and measure its

voltage VDD(meas) as accurate as possible with the multimeter. Calculate the gate DC

voltage VG(cal) using the voltage-divider rule.

4. Measure the DC voltages VG, VD and VS at G, D, and S pins of the transistor as accurate as

possible. Note that the measured VG should be closed to the calculated VG(cal), and VS

should be >VG since VGS must be < 0 V for N-channel JFET.

5. Before connecting the function generator to the circuit, use an oscilloscope to measure the output voltage of the generator and set it to 200 kHz sine-wave with a peak-to-peakvoltage of 0.1V. Press the attenuation button (ATT) of the generator for easy adjustment of its output voltage.

6. Connect the generator output to the circuit. Using Channel 1 (CH1) of the oscilloscope (set at AC input coupling), probe the input voltage vin. Using Channel 2 (CH2) of the

oscilloscope, probe the load resistor RL, as shown in Figure 5. Set the trigger source of the

oscilloscope to CH2. Adjust the trigger level on the oscilloscope to obtain stable waveforms. Make sure the variable (VAR) knobs of the oscilloscope are set at the calibrated (CAL’D) positions.

Figure 5: A Common source JFET amplifier

7. Adjust the Volts/div and Time/div to display the waveforms on the oscilloscope screen as big as possible with one to two cycles. Sketch the input AC voltage (vin) and

the load voltage (vL) waveforms on the graph. Record the Time/div and Volts/div used.

Note that the input and output waveforms should be approximately 180o out of phase.

8. From your graph, determine VL(pp) and Vin(pp) which are the peak-to-peak voltages ofvL and

vin, respectively. Calculate the voltage gain (Av) of the JFET amplifier circuit at 200

kHz.Ask the instructor to check all of your results. You must show the oscilloscope waveforms to the instructor.

9. Sweep the frequency of the function generator from 1 kHz to 550 kHz (use smaller frequency steps near the half-power point while larger steps can be used at mid-band frequencies). Record the peak-to-peak voltages of vin (CH1) and vL (CH2) and calculate

the dB magnitude of the voltage gain Av. Use both coarse and fine adjustment knobs of

the function generator for frequency adjustment. 10.Plot a curve of Av versus frequency.

11.Calculate the lower cutoff frequency fLD(cal) (use the measured RD and RL values). Set the

frequency to 20 kHz. To measure the lower cutoff frequency (fLD), decrease the generator

frequency until VL(pp) decreases to 0.707VL,mid-band(pp), where VL,mid-band(pp) is the VL(pp) value

in the mid-band.

12.Set the frequency to 300 kHz. To measure the upper cutoff frequency (fHD), increase the

generator frequency until VL(pp) decreases to 0.707VL,mid-band(pp).

13.Determine the bandwidth (BW) and the geometric center frequency (fo) of the amplifier

from the above measurements. Ask the instructor to check all of your results. You must show the oscilloscope waveforms at 550 kHz to the instructor.

14.Design or modify the circuit in Figure 5 in order to measure the parameter of the device, namely Gate-Source Cutoff Voltage (VGS(off) or Vp) and Zero-Gate Voltage Current (IDSS).

These two values can be used in the Shockley equation ID = IDSS(1 – VGS/Vp)2 . Hint: You

can use a potentiometer and/or negative power source in the circuit. By solving the simultaneous equation of the Shockley equation and the load line equation, you can obtain the calculated value for the Q point VGSQ, VDSQ, IDQ. . Compare this with the

measured value. +VDD=12V R1=22kΩ CG=0.47µF 50Ω Vgen _{R2 =10k}Ω RD=3.3kΩ CD=0.01µF CS=0.47µF RL=10kΩ RS=3.9kΩ Function Generator G D S 0.1µF CH2 (vL) CH1 (vin) D S G

APPENDIX A

Log Scale

The distance in a decade of the log scale in the figure below is x mm. Since log101 = 0, it is

used as a refernce point (0 mm) in the linear scale. Then, the reading 10 is located at x mm and the reading 0.1 is located at –x mm. For a reading F, it is located at [1og10(F)]*x mm.

E.g.:

Reading 0.25 is located at [1og10(0.25)]*x mm = -0.602x mm

Reading 2.5 is loacted at [1og10(2.5)]*x mm = 0.398x mm

Reading 25 is located at [1og10(25)]*x mm = 1.398x mm (not shown in the figure)

Reading 250 is located at [1og10(250)]*x mm = 2.398x mm (not shown)

Conversely, a point at z mm location is read as 10z/x. E.g.:

-0.3x mm is read as 10(-0.3x/x)= 0.501 0.6x mm is read as 10(0.6x/x)= 3.98

1.5x mm is read as 10(1.5x/x)= 31.6 (not shown) 2.7x mm is read as 10(2.7x/x)= 501 (not shown)

9 0.1 0.2 0.3 0.5 1 2 3 5 10 -x 0 x Linear scale (mm) Log scale (unit) 0.25 2.5 0.398x -0.602x 0.6x 3.98 0.501 -0.3x 0.4 0.6 0.7 0.8 0.9 4 6 7 8

The Resistor color code chart

ABC AB x 10C pF .abc 0.abcµµµµF Capacitance Potentiometer A Var B

Appendix B: Breadboard Internal Connections

Vertically

connected

Vertically

connected

Horizontally connected

Horizontally connected

+VCC 0V GND 555 1 2 3 4 8 7 6 5

General mistakes:

The legs of the resistors and the transistor are shorted

by the breadboard internal connections.

MultimediaUniversity FOE 0.1 µµµµF

Internal

connections

Internal

connections

STUDENT'S NAME:

ID NO:

SUBJECT CODE AND TITLE: EEE1026 ELECTRONICS 2

EXPERIMENT TITLE: EB1 - FET Amplifier Frequency Response

EXPERIMENT DATE: TIME:

Criteria 1 (Need Improvement) 2 (Satisfactory) 3 (Good) 4 (Excellent)

Rating Awarded by Assessor

Data Collection and Setting up the Experiment

1 Ability to construct the amplifier circuit on the breadboard

Unable to construct the amplifier circuit, and not asking for help.

Able to construct the amplifier circuit partially.

Able to construct the amplifier circuit.

Able to construct the amplifier circuit correctly, with neat and tidy placement of components and jumper wires

2 Ability to set-up the power supply for the circuit, the function generator to the amplifier and to connect the oscilloscope to display the waveform

Unable to setup the DC or AC input to the amplifier, and not asking for help.

Able to setup the DC and AC input to the amplifier partially.

DC and AC input to the amplifier is correctly setup.

DC and AC input to the amplifier is correctly setup and the waveforms are visible in the oscilloscope.

Analysis and Conclusions

3 Ability to extract the mid-band amplifier's

characteristics.

No voltage gain is observed, and not asking for help.

No voltage gain is observed, but the waveforms are approximately at opposite phase.

Voltage gain is more than unity, with the input and output at approximately opposite phase.

The voltage gain is fair, with the input and output at opposite phase.

4 Ability to extract the amplifier's complete frequency response.

There is no difference between the low-, mid- and high-frequency response of the amplifier.

Minor differences between the low-, mid- and high-frequency response of the amplifier.

Low-, mid- and high-frequency response of the amplifier shows some difference.

Low-, mid- and high-frequency response of the amplifier is clearly seen on a graph.

5 Ability to answer the questions in by Oral Assessment

Not able to answer the question, no attempt was made to answer

Able to answer questions with some basics answers and demonstrate some attempts to refer to the text books, notes, lab sheet

Able to answer most part of the questions, with some explanations and elaborations and demonstrate some attempts to refer to text books, notes or lab sheet

Answered all correctly with proper explanations and elaborations, without a need to refer to any references.

Lab Report

(Submit your report on the same day immediately after the experiment) Name: ________________________Student I.D.: _______________Date: __________

Majoring: ____________________ Group: ____________ Table No.: ____________

1. Table E1: Measured resistance values 1

R R₂ R_D R_S R_L

[5 marks] 3. VDD(meas) = ________ V, VG(cal) = ________ V [2 marks]

4. Table E2: Measured DC voltages

G

V V_D V_S

[3 marks] 7. Graph E1: vin and vL waveforms at 200 kHz

Time base : ______ s/div, CH1 (vin) : ______ V/div, CH2 (vL) : ______ V/div

[5 marks] 8. = = ) ( ) ( pp in pp L v V V A ________ at 200 kHz [1 mark]

CH1 & CH2

ground

2 9. Table E3: Measure VL(pp) and Vin(pp), and calculated AV

f /kHz 1 2 5 10 20 40 60 80 100 200 500 550

VL(pp) /V

Vin(pp) /V

Av(dB)

[6 marks] 10. Graph E2: Av versus frequency

[5 marks] 11.

(

L D

)

D cal LD C R R f + = π 2 1 ) ( = _________ Hz ) (meas LD f = _________ Hz 12. f_HD(meas) = _________ kHz 13. BW = fHD – fLD = _________ kHz HD LD o f f f = = _________ kHz [5 marks]

3 1. Identify the sources of error in the calculated VG(cal).

________________________________________________________________________ ________________________________________________________________________

2. Calculate the actual DC currents flowing through RD and RS, respectively, IRD and IRS

(calculation steps must be included). Explain why they are the same.

________________________________________________________________________ ________________________________________________________________________

3. What is the measured Q-point value (VGSQ, VDSQ, IDQ) of the JFET amplifier circuit?

Analyze and compare this with the calculated one.

________________________________________________________________________ ________________________________________________________________________

4. Estimate the lower cutoff frequency of the input circuit, fLG (show your calculation steps).

________________________________________________________________________

5. Estimate the total output capacitance which determines the upper cutoff frequency fHD

________________________________________________________________________

[15 marks]

Discussion

1. Identify how the vin and vL waveforms in Step 7 are related in terms of positive and

negative peak voltages, waveform shapes and phase shift.

________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________

4 2. Describe the Av versus frequency characteristic.

________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________

3. Explain the difference between the calculated fLD(cal) and the measured fLD.

________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________

4. Propose why fHDcannot be calculated and as to what factor determines this fHD.

________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ [16 marks] Conclusion ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ ___________________________________________________________________________ __________________________________________________________________________. [7 marks]