A REVIEW OF SOME POPULAR HARDWARE IMPLEMENTATION TECHNIQUES IMPLEMENTED ON ADVANCED ENCRYPTION STANDARD

(1)

A REVIEW OF SOME POPULAR HARDWARE

IMPLEMENTATION TECHNIQUES IMPLEMENTED

ON ADVANCED ENCRYPTION STANDARD

Vishnu Suryawanshi

1

, Sachin Ahankari

2

, Dr. G. C. Manna

3

1

E&Tc, GHRIET, (India),

2

E&Tc, IOKCOE, (India)

3

D.M, BSNL, Jabalpur, (India)

ABSTRACT

This review Research paper concentrates on the different kinds of hardware implementation techniques that are

exist. It also frames all the hardware implementation techniques together as a literature survey. The main Aim is the

practical study of hardware implementation Techniques on Advanced Encryption Standard with the basis of various

available encryption methods. Also it focuses on Throughput, Latency, Memory Size and Cipher’s Encryption Speed.

This study extends to the performance parameters used in Hardware Implementation Techniques and analyzing how

the techniques can be implemented to improve the security of AES Cipher.

[[

Keywords: Cryptography, AES, FPGA, Hardware Implementation Techniques.

I INTRODUCTION

Security of the messages is the main concern in communication applications. Considering the Need of message

secrecy, cryptography concept is introduced. Cryptography is a Greek word for “hidden writing”. Cryptography is

the study of how to design algorithms that provide confidentiality, authenticity, integrity and other security related

services for data transmitted in insecure communication environments.

Advanced Encryption Standard (AES) is a specification for the encryption of electronic data. It has been adopted by

the US Government and is now worldwide. It supersedes DES (Data Encryption Standards).In the United States, AES

was announced by National Institute of Standards and Technology (NIST). On November 26, 2001 before five years

standardization process in which fifteen competing designs were presented and evaluated. AES is the first publically

accessible and open cipher approved by National Security Agency (NSA) for top secret information. As the

technology grew DES was not enough to give sufficient security.

Rijndael (the cipher was developed by two Belgian cryptographers Joan Daemen and Vincent Rijmen) became the

new AES in October 2000 because of its enhanced security levels. Rijndael used in 3G (3rd Generation), 3GPP (3rd

Generation Partition Project). Rinjdael is based on design principle known as a substitution-permutation network,

(2)

bits [1].It offers a good combination of security, performance, efficiency, implement ability and flexibility [2]. AES

operates on a 4x4 array of bytes (referred to as “state”). The algorithm consists of following four different simple

operations.

These operations are:

1. Sub Bytes

2. Shift Rows

3. Mix Columns

4. Add Round Key

Details of the AES encryption round function

Sub Bytes perform byte substitution which is derived from a multiplicative inverse of a finite field.

Shift Rows shifts elements from a given row by an offset equal to the row number.

Mix Columns step transforms each column using an invertible linear transformation.

Add Round Key step takes a 4x4 block from a expanded key (derived from the key), and XORs it with the “state”.

AES is composed of four highlevel steps.

These are:

1. Key Expansion

(3)

3. Rounds

4. Final Round

II. LITERATURE SURVEY

Numerous proposals have addressed for high speed hardware implementation of the AES algorithm. Some of the

proposals have focused on an ASIC [3, 4] implementation where others have been targeted FPGAs [5, 6]. Number of

techniques has been used to implement the AES algorithm in hardware. Lookup table based hardware implementation

is shown in [7]. The pipeline approach increases the throughput by processing multiple blocks of data

simultaneously [8]. The main difference between sub-pipelining and pipelining is the division of a single round or a

single operation, which is a single pipeline stage, into several sub-operations or sub-pipeline stages reducing the

inter-stage gate delays and increasing the operating frequency of the sub-pipeline. Loop unrolling [9] is the opposite

of pipelining where several operations and even rounds are sequentially processed using combinational logic within

a single clock cycle.

Evaluating the characteristic performance of AES-128 bit in terms of pipelined hardware implementation which

shown a competitive throughput of more than 2G bits per second .has been implemented by Nadia Nedjah, Luiza de

Macedo Mourelle , Marco Paulo Cardoso in (2006) [10]. Throughput = 128/(average number of clock cycles to

process one block x clock period).Paolo Maistri, Régis Leveugle (2011) presents a performance evaluation on

throughput, their evaluation is based on heavy pipelining and partial unrolling which is capable of a 10-Gbps

throughput when encrypting with 128-bit keys. Moreover they about the design robust against known attacks, such

as differential power analysis (DPA) or fault attacks [11]. Nalini C, Nagaraj, Dr. Anandmohan P.V presented a

paper which is an efficient solution to combine Rijndael encryption and decryption in one FPGA design, with a

strong focus on low area constraints and high throughput (30.88Gbps) with a frequency of 242.3 Mhz. and 4626

CLB Slices with 160 BRAM’S. in non-feedback modes, which is faster and more efficient [12].

In 2010 Cheng Wang and Howard M. Heys presented a paper which shows area and speed performance applying a

pipelined S-box to compact AES hardware implementations has been examined. The design employs a single

4-stage pipelined S-box that is shared by the data path operation and the key expansion operation [13]. Samir El Adib

and Naoufal Raissouni (2012) jointly presented the architecture which uses memory modules (i.e. Dual-Port RAMs )

of Field-Programmable Gate Array (FPGAs) for storing all the results of the field operations (i.e. Look-Up Table)

and Digital Clock Manager (DCM) that can be used effectively to optimize the execution time, reduce the design

area and facilitates implementation in FPGA. The architecture consumes only 326 slices and 3 block Random

Access Memory (BRAMs). The throughput obtained was of 270 Mbits/s.The presented architecture can be used in a

wide range of embedded applications [14]. Tuan Anh Pham, Mohammad S. Hasan and Hongnian Yu (2012)

presented a paper which shows an optimised area and power implementation of the AES-128 encryption algorithm

is presented on FPGA. Regarding the constraints of resource occupancy and low-power requirement, the design is

(4)

coding, clock gating. The results of the simulation and verification have shown a very compact circuit of 277 logic

elements and 5.88mW energy dissipation [15].

Mr. Atul M. Borkar Dr. R. V. Kshirsagar Mrs. M. V. Vyawahare presented a paper that determines The parameter

that compares AES candidates from the point of view of their hardware efficiency is Throughput. Encryption /

Decryption Throughput = block size frequency / total clock cycles. Thus, Throughput = 128 x 140.390MHz/51 =

352 Mbits/sec. for both encryption and decryption process with Device XCV600 of Xilinx Virtex Family.,the

Maximum Operating Frequency 140.390 Mhz and the total memory use is 130248 kilobyte [16]. In 2007 James S.

Grabowski and Amr Youssef presented a paper where most of the common implementations that support only ECB

mode,our design supports five modes of operation. In particular, it supports ECB, CBC, CFB, OFB and CTR modes.

The design occupies 7452 slices of a Xilinx Virtex-II Pro XC2VP50, features a maximum clock speed of 56.3MHz

and produces throughput up to 480.427 Mbps, 423.906 Mbps and 379.284 Mbps for 128,192 and 256-bit keys

respectively [17,18].

Encryption modes of operations

.

ECB: (Electronic Code Book).

CBC: (Cipher-Block Chaining).

OFB: (Output Feedback).

CFB: (Cipher Feedback).

CTR: (Counter).

(5)

III.RINJDAEL-ALGORITHM

IV. CONCLUSION

In this paper the existing hardware implementation techniques are studied and analyzed to promote the performance

of the hardware implementation techniques to ensure the Throughput, Latency, Memory Size and Cipher’s

Encryption Speed. To sum up, all the implementation techniques are useful for real time implementation. Each

technique is unique in its own way, which might be suitable for different parameters. Everyday new hardware

implementation technique is evolving hence fast and secure conventional encryption implementation techniques will

always work out with high rate of security.

REFERENCES

[1] J. Daemen and V. Rijmen, "AES Proposal: Rijndael. NIST AES Proposal," June 1998. Available at

http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf.

[2] A. Rudra, P.K. Dubey, C.S. Jutla, V. Kumar, J.R. Rao, P. Rohatgi, "Efficient Rijndael encryption

implementation with composite field arithmetic," Lecture Notes in Computer Science 2162 (2001) 171–184.

[3] Kotturi, D.; Seong-Moo Yoo; Blizzard, J.; “AES Crypto Chip Utilizing High-Speed Parallel Pipelined

Architecture”, IEEE International Symposium on Circuits and Systems, ISCAS2005. 23-26 May 2005

Page(s):4653 - 4656 Vol. 5

[4] Xinmiao Zhang; and K.K. Parhi, “High-Speed VLSI Architectures for the AES Algorithm”, IEEE Transactions

(6)

[5] K. U. Jarvinen, M. T. Tommiska, and J. O. Skytta, “A fully pipelined memoryless 17.8 Gbps AES-128

encryptor,” in Proc.Int. Symp. Field-Programmable Gate Arrays (FPGA 2003), Monterey, CA, Feb. 2003, pp.

207–215.

[6] G. P. Saggese, A. Mazzeo, N. Mazocca, and A. G. M. Strollo, “An FPGA based performance analysis of the

unrolling, tiling and pipelining of the AES algorithm,” in Proc. FPL 2003, Portugal, Sept. 2003.

[7] M. McLoone and J. V. McCanny, “Rijndael FPGA implementation utilizing look-up tables,” in IEEE

Workshop on Signal Processing Systems, Sept. 2001, pp. 349–360.

[8] X. Zhang and K. K. Parhi, “Implementation approaches for the advanced encryption standard algorithm,”

IEEE Circuits Syst. Mag., vol. 2, no. 4, pp. 24–46, 2002.

[9] K. Gaj and P. Chodowiec. “Comparison of the hardware performance of the AES candidates using

reconfigurable hardware”. Presented at Proc. 3rd AES Conf. (AES3).

[10] Nadia Nedjah, Luiza de Macedo Mourelle , Marco Paulo Cardoso “A Compact Piplined Hardware

Implementation of the AES-128 Cipher” Proceedings of the Third International Conference on Information

[11] Paolo Maistri, Régis Leveugle “10-gigabit Throughput and Low Area for a Hardware Implementation of the

[12] Nalini C, Nagaraj, Dr. Anandmohan P.V*, & Poornaiah D.V, V.D.kulkarni “An FPGA Based Performance

[13] Cheng Wang and Howard M. Heys “Using a Pipelined S-Box in Compact AES HardwareImplementations”

[14] Samir El Adib and Naoufal Raissouni “ AES Encryption Algorithm Hardware Implementation Architecture:

Resource and Execution Time Optimization” International Journal of Information & Network Security (IJINS)

Vol.1, No.2, June 2012, pp. 110~118 ISSN: 2089-3299

[15] Tuan Anh Pham, Mohammad S. Hasan and Hongnian Yu “Area and Power optimisation for AES encryption

module implementation on FPGA” Proceedings of the 18th International Conference on Automation &

Computing, Loughborough University,Leicestershire, UK, 8 September 2012

[16] Mr. Atul M. Borkar, Dr. R. V. Kshirsagar and Mrs. M. V. Vyawahare “FPGA Implementation of AES

[17] James S. Grabowski and Amr Youssef “An FPGA Implementation of AES with Support for Counter and