International Journal of Advanced Engineering Science and Technological Research (IJAESTR)
Simulation and Implementation of Three-Phase Multilevel Inverter
Sandeep Gupta1, Mrs. Shimi S.L.2, Dr. (Mrs.) Lini Mathew3 , Swati Singh4
1Research Scholer[ME], Department of EE, NITTTR,Chandigarh, India
2Assistant Professor, Department of EE, NITTTR,Chandigarh, India
3Professor and Head, Department of EE, NITTTR,Chandigarh, India
4Assistant Professor, Department of ECE, MIT,Meerut, India E-mail ID [email protected]
Abstract— This paper presents a new three-phase five-level fifteen switches voltage source inverter. The proposed topology is based on insertion of nine bi-directional switches between the source and the full-bridge power switches of simple three-phase inverter. A five-level output voltage waveform and low total harmonics content are obtained at the multilevel inverter output.
A Fourier analysis of the output voltage waveform is performed and firing angles are optimized to obtain the minimum load harmonics contents. The proposed system has been analysed and simulated via MATLAB/SIMULINK environment. To validate the proposed work, a prototype inverter is developed and tested with four battery 12Volts) as DC sources.
Index Terms- Five-level inverter, Multi level inverter, Total harmonics distortion, Five level output waveform inverter.
I. INTRODUCTION
Multilevel inverters are commonly used for applications in medium and high power conversion systems. This concept was first introduced in 1976 and later it was used with grid- connected cells in 1990s. In the recent development of multilevel inverters, the prime focus is on to get clean sinusoidal waveform with minimum THD and increase power conversion without increasing voltage stress on switches. The requirement of minimum harmonics content in output voltage is increased due to high standards applied to electrical energy.
There are many of multilevel inverters; mainly three of them are well known: the neutral point clamped (NPC), the flying capacitor (FC), and the cascaded H-bridge[21]. All the other topologies [10-16] are modifications of those topologies. Many three-phase loads require a supply of variable voltage at a variable frequency. Generally it is preferred to get three-phase ac supply from a dc source. The dc power inputs are power supply network or rotating alternator through rectifier, fuel cell, or photovoltaic array.
This paper proposes a multilevel inverter where the dc source is taken from storage battery bank. Section II explains the general block diagram and operating principle of proposed multilevel inverter. Section III describes an analysis of THD control method for inverter output waveform and a comparison is given with other five-level multilevel three phase inverters.
To serve as a reference for the validity of inverter, section IV gives MATLAB/SIMULINK simulated results and hardware implementation of a prototype inverter. The results are used for verifying performance of multilevel inverter. Subsequently in section V summarizes the proposed inverter concept presented in the paper.
II. THE PROPOSED MULTILEVEL TOPOLOGY A. General Description
The circuit diagram of the proposed three-phase five- level inverter is shown in Fig.2 which consists of four isolated and regulated dc sources (Vs), nine bi-directional switches and an isolated H-bridge of conventional two-level three-phase inverter The bi-directional switches are represented by S1, S1a, S1b, S2, S2a, S2b, S3, S3a, and S3b. The conventional H-bride circuit have six main switches and represented by Q1, Q2, Q3,
Q4, Q5, and Q6. The phase currents are represented by ia, ib, and ic.
Fig. 2 The Proposed Fifteen Switches Five-Level Inverter
B. Operating Principal
Fig. 3 shows the proposed firing pulses of the power switches, where the modes can be divided into 25 switching states. The on/off states of the switches are shown in Table 1.
Fig. 3 Switching Timing Diagram
The two operation modes are illustrated in Fig. 4(i) and (ii).
The operating modes can be described as follows:
Fig.4(i) Mode i: Van = Vbn = 0, and Vcn = 4Vs
Table 1 Switching States of Switches in each Step Duration
Mode i: For switching duration time ∆t1, only switches Q2, Q3, and Q4 are in the on-state and all the other switches are in the off-state; i.e; Van = Vbn = 0, and Vcn = 4Vs, which means that both load nodes a and b are connected to the neutral point N of the dc bus, while load c is connected to the top point of the dc bus as shown in Fig.4 (i).
Mode ii: For switching duration time ∆t2, only switches S1, Q3, and Q4 are in the on-state and all the other switches are in the off-state; i.e; Van = Vs, Vbn = 0, and Vcn = 4Vs, which means that both load nodes a and b are connected to the neutral point N of the dc bus, while load c is connected to the top point of the dc bus as shown in Fig.4 (ii).
International Journal of Advanced Engineering Science and Technological Research (IJAESTR) Fig.4(ii) Mode ii: Van = Vs, Vbn = 0, and Vcn = 4Vs
In all the other modes, different levels are obtained as given in Table 1. It is observed in different modes that the direction of load currents depends on voltages.
III. ANALYSIS OF OPTIMIZED WAVEFORM Fig.5 illustrates the load phase voltages Van, Vbn, and Vcn
referred to the neutral point of the dc bus. If neutral point 'n' of the dc bus is not connected to the neutral point of the load 'N', the phase voltages of the load are related to the neutral point of the dc bus 'n'.The line-to-line load voltage Vab can be obtained using the equation: Vab = Van-Vbn. The line-to-line voltage waveform as shown in Fig. 5 is known as a stepped waveform.
A Fourier analysis of this waveform gives the magnitudes of the harmonics as a function of α and β. The ideal is to get a clean sinusoidal output voltage, i.e., the content of the harmonics orders greater than one (n=3, 5, 7 …) should be zero. The THD of the output voltage is defined as the ratio of all harmonic components’ rms value to the fundamental component’s rms value.
Fig. 5 Waveforms of the Load Node Voltages Van, Vbn, Vcn and Line-to-Line Voltage Vab
A computer simulation of the THD as a function of the parameters of α and β is done, where the minimum THD (THD < 9.25%) is obtained for α= 7° and β= 16°. Table 2 gives a comparison between the proposed inverter and the well-known five-level inverters: diode-clamped, flying capacitor, cascaded inverter and other topologies. it can be concluded that the proposed multilevel inverter produce the same output voltage waveform with minimum number of switches hence less switching losses and low THD in inverter output voltage waveform.
Ref. No. Topology Name Abbreviation No. of sources
No. of switches
No. of Clamping
Diodes
No. of flying capacitors
Neutral
Neutral point clamped NPC 1 2 24 18 0 Y
Flying capacitor FC 3 24 0 1 8 N
Cascaded H-bridge converters CHB 6 24 0 0
[12] Rotating switch back to back multilevel inverter
MNP 1 2 24 0 0 Y
[13] Level and H-Bridge inverter — 6 2 4 0 0
[11] Diode bypassed multilevel dc-link inverter
— 6 18 6 0 N
Diode bypassed neutral point inverter
— 1 2 1 8 1 8 0 Y
[10] Series parallel switched multilevel dc- link inverter
SPMLDCL 6 18 3 0
[15] Hybrid capacitor-clamp cascade multilevel converter
HCCMC 6 24 0 1 2
[05] H-bridge diode-clamped cascade multilevel inverter
HDCMC 6 24 1 2 0
The proposed multilevel inverter — 4 15 0 0 Y
Table 2 Comparison of Five-Level Topologies
IV. RESULT AND DISCUSSION
The proposed topology has been simulated using MATLAB/SIMULINK to verify the performance of the proposed configuration.
The complete SIMULINK model of proposed multilevel inverter is shown in Fig. 6.
Vs Vs Vs Vs
Three-Phase V-I Measurement
Three-Phase Load
A B C
A B C
C ontinuous powe rgui
+v -
+v - +v -
+v - +v - +v -
+v - +v - +v -
VcN To Workspace9
VbN To Workspace8
VaN To Workspace7
Vcn To Workspace6
Vbn To Workspace5
Van To Workspace4
Vca To Workspace3
Vbc To Workspace2 t
To Workspace1
Vab To Workspace
Va bc Ia bc A
B
C a b c Out1
Out2
Out3
Out4
Out5
Out6
Out7
Out8
Out9
Subsystem1
Out1
Out2
Out3
Out4
Out5
Out6
Subsystem
Scope9 Scope8
Scope7 Scope6 Scope5 Scope4 Scope3 Scope2
Scope10 Scope1
gm CE
gm CE
gm CE gm CE
gm CE
gm CE
gm CE
gm CE
gm CE
[S3b]
Goto9 [S3a]
Goto8 [S3]
Goto7 [S2b]
Goto6 [S2a]
Goto5 [S2]
Goto4 [S1b]
Goto3 [S1a]
Goto2
[Q6]
Goto15 [Q5]
Goto14 [Q4]
Goto13 [Q3]
Goto12 [Q2]
Goto11 [Q1]
Goto10 [S1]
Goto1
[S3b]
From9..
[S3a]
From8..
[S3]
From7..
[S2b]
From6..
[S2a]
From5..
[S2]
From4..
[S1b]
From3..
[S1a]
From2..
[Q6]
From15 [Q5]
From14.
[Q4]
From13.
[Q3]
From12..
[Q2]
From11.
[Q1]
From10..
[S1]
From1 amk
amk ma
k
ma k amk
amk
amk
ma k
ma k
amk
amk mk a
ma k ma k
amk
amk
ma k
ma k
amk amk
ma k
ma k
a mk a mk ma k
ma k
ma k amk
amk ma
k
ma m k
a k
amk ma
k
ma k amk
Clock
gm CE
gm CEgm CEgm CEgm CE
gm CE
Fig.6 Simulink Model for Three Phase Five Level Multilevel Inverter
International Journal of Advanced Engineering Science and Technological Research (IJAESTR) A balanced three-phase star connected RL load with 30Ω
resistance, and 50mH inductor per phase was used. Fig. 6 shows the inverter output waveforms of the load node voltages Van, Vbn, and Vcn.
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
-50 0 50 100 150 200 250
Time[sec]
Van[V]
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
-50 0 50 100 150 200 250
Time[sec]
Vbn[V]
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
-50 0 50 100 150 200 250
Time[sec]
Vcn[V]
Fig. 7 MATLAB SIMULINK simulated waveforms of the load node voltages Van, Vbn and Vcn.
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
-200 -150 -100 -50 0 50 100 150 200
Time[sec]
Vab[V]
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
-150 -100 -50 0 50 100 150
Time[sec]
VaN[V]
Fig. 8 MATLAB SIMULINK Simulated Waveforms of: (a) The Line-to-Line Voltage Waveform Vab and (b) The Load Phase Voltage Waveform VaN.
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
-250 -200 -150 -100 -50 0 50 100 150 200 250
Time[sec]
Vbc[V]
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
-150 -100 -50 0 50 100 150
Time[sec]
VbN[V]
Fig. 9 MATLAB SIMULINK Simulated Waveforms of: (a) The Line-to-Line Voltage Waveform Vbc and (b) The Load Phase Voltage Waveform VbN.
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
-250 -200 -150 -100 -50 0 50 100 150 200 250
Time[sec]
Vca[V]
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
-150 -100 -50 0 50 100 150
Time[sec]
VcN[V]
Fig.10 MATLAB SIMULINK Simulated Waveforms of: (a) The Line-to-Line Voltage Waveform Vca and (b) The Load Phase Voltage Waveform VcN.
The Total Harmonic Distortions of the line voltage and the phase voltage, which is 9.25% and 9.21% respectively are shown in Fig. 11 and Fig.12.
0 100 200 300 400 500 600 700 800 900 1000
0 0.5 1 1.5 2 2.5 3 3.5 4
Frequency (Hz) Fundamental (50Hz) = 208.3 , THD= 9.25%
Mag (% of Fundamental)
Fig. 11 THD of the Line-to-Line Voltage Vab
0 100 200 300 400 500 600 700 800 900 1000
0 0.5 1 1.5 2 2.5 3 3.5
Frequency (Hz) Fundamental (50Hz) = 120.5 , THD= 9.21%
Mag (% of Fundamental)
Fig. 12 THD of the Phase Voltage VaN
Fig. 13 shows SIMULINK diagram of the whole system with LC filter. The filter components are 0.5mH and 10μF. The resistive load is 25 Ω. Four independent DC voltage sources, each having output voltage of 50 V.
Continuous powergui
Vdc3 Vdc2 Vdc1 Vdc
+v - Vca +v - Vbc +v - Vab t
To Workspace
upper bridge S1b S2b S3b S1a S2a S3a S1 S2 S3 lower bridge
a
b
c
Three-Phase Multilevel Inverter
Vabc Iabc A B C
a b c Three-Phase V-I Measurement
Scope4 Scope3 Scope2 Scope1
A B C A B C
R= 25Ohm A
B C A B C L=500mH Clock
A B C
A B C
C= 10mF
Fig. 13 Three-Phase Multilevel Inverter with LC Filter
Fig. 14 shows the simulated output line voltage waveforms. The waveforms for line voltages are almost sinusoidal and smooth;
the phase-difference is kept constant at 120 degree.
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
-400 -300 -200 -100 0 100 200 300 400
Time(msec)
Magnitude
Three Phase Voltage
Fig. 14 Output Line Voltages of Inverter with Filter
The Total Harmonic distortions of the line voltage is 1.97% as shown in Fig. 15.
Fig. 15 THD of the Line-to-Line Voltage Vab
To validate the proposed topology, a prototype of the three phase five-level inverter is developed in the laboratory. The schematic diagram is shown in Fig. 16.
Fig. 16 Schematic diagram of the experimental setup.
International Journal of Advanced Engineering Science and Technological Research (IJAESTR) The triggering gate pulses for a 5-level inverter are simulated
using Xillinx 12.1 and implemented on an Xillinx (Spartan-6) XC6SLX25T FPGA [20] whose crystal frequency is 100MHz.
Fig. 17 shows the gating pulses to the switches of the proposed inverter..
Fig. 17 Gate pulse generated for five level inverter using Xillinx 12.1 ISE.
A Picture of the switch module (one of 5 modules) has shown in Fig. 18 (a) and picture of prototype inverter is depicted in Fig. 18(b). MOSFETs (IRF840) driven with gate drivers MIC 4426 are used as power switches in the prototype.
Fig. 18(a) Constructed main switch module (one of 5 modules)
Fig. 18(b) Picture of 5-level prototype of three phase inverter with the drivers integrated to the switch modules.
Four batteries with equal voltages (12V) are used as dc sources for experimental set-up. The inverter is loaded with three phase resistive load with R = 22 Ω. The control scheme is implemented through a FPGA board (Spartan-6) [18]. The load voltage obtained at the inverter terminals is shown in Fig.
18. The voltage waveform and its THD are in close agreement with respective simulations results. A close agreement with the simulation results can be observed. The THD in this case is 11.23%.
Fig. 19 Output voltage Vab
V.CONCLUSION
In this work, a three-phase five-level fifteen switch voltage source inverter is simulated and implemented using FPGA. In this topology, an additional auxiliary circuit which consists of nine bi-directional switches has been inserted between the source and the full-bridge power switchs of the classical three- phase inverter. As a result, a significant reduction of the load harmonics contents is obtained at the inverter output. Its operating principles and switches timing chart based on harmonic minimization control schemes are analyzed in detail.The simulation and experimental results show that THD of the proposed inverter has been considerably improved.
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