Abstract— Reducing the area and power of 64 bit modified square root Carry Select Adder (SQRT CSLA) when compared to conventional CSLA and binary to excess-1 converter (BEC)-based SQRT CSLA. The logic operations involved in conventional carry select adder (CSLA) and BEC based SQRT CSLA are analyzed to study the data dependence and to identify redundant logic operations. In this paper all the redundant logic operations present in the conventional CSLA have been eliminated and proposed a new logic formulation for CSLA. The new logic formulation is based on data dependence and optimized carry generator (CG) and carry select (CS) design. Using these optimized logic units, an efficient design is obtained for the CSLA. In the modified scheme, final-sum calculation is scheduled before the operation of carry select, which is different from the conventional approach. The modified SQRT CSLA design involves significantly less area and power than conventional SQRT CSLA and BEC-based SQRT CSLA. The implementation of a 4 bit modified Square Root Carry Select Adder and its capability of extending its word size to 8, 16, 32, 64 bits.
INDEX TERMS
Binary to excess-1 converter, conventional carry select adder, carry select, carry generator and Carry Select Adder.
I.INTRODUCTION
Adders are most important in VLSI designs and it is used in computer, in multipliers, in high speed integrated circuits and in digital signal processing [1]. Low power, area efficient and high-performance based VLSI systems are
Manuscript received, Feb , 2016.
SHEEBA A1currently working as Assistant Professor in ECE Department at Dr.Sivanthi Aditanar College of Engineering, Tiruchendur She received her ME Degree in Communication Systems From Francis Xavier Engineering College, under Anna University Chennai and her BE Degree in ECE from Dr.G U Pope College of Engineering, under Anna University Chennai.
MANGALA MARISELVI E2 and ANITHA K3received her Bachelor of Engineering degree in Electronics and Communication Engineering from Dr.Sivanthi Aditanar College of Engineering under Anna University, Chennai. Currently pursuing Master of Engineering in Very Large Scale Integration (VLSI) from Dr.Sivanthi Aditanar College of Engineering under AnnaUniversity,Chennai
increasingly used in portable, in mobile devices, in wireless receivers, and in biomedical instrumentation [2].
An adder is the basic component of an arithmetic unit.
Several adders have been used in complex digital signal processing systems. The performance of complex DSP system is improved by an efficient adder design. A ripple carry adder (RCA) design is simple, but carry propagation delay is main concern. Carry look-ahead adder and carry select adder have been suggested to reduce the carry propagation delay.
In digital adders each bit position is added as the sum and generated the carry is propagated into the next position [3]. In RCA, the propagated carry reduces the speed of addition. So the carry select adder is used to overcome this problem. Carry select adder is one of the fastest adders having less area and power consumption. A CSLA has less CPD than an RCA, but the CSLA design is not attractive since it uses a dual RCA.
1.1 CARRY SELECT ADDER (CSLA)
The Carry Select Adder (CSLA) generally consists of two set of ripple carry adders and multiplexer. Two n-bit numbers are added with a carry-select adder is done with two set of ripple carry in order to perform the calculation twice, one time with the assumption of the carry input being zero and the other assuming carry input being one. After the two results are calculated, then output of correct sum and correct carry is selected with the multiplexer once the correct carry input is known. Figure 1 shows, basic building block of 4 bit Carry Select Adder.
Figure 1 Basic building block of 4 bit carry select adder
LOW POWER AND AREA EFFICIENT 64 BIT MODIFIED CARRY SELECT
ADDER
A.Sheeba 1 , E.Mangala MariSelvi 2 , K.Anitha 3
Carry select adder is classified into two types:
(i) Linear CSLA (ii) Square root CSLA 1.2 LINEAR CSLA
Linear CSLA can be implemented by chaining a number of equal length adder stages. For n bit adder, it could be implemented by equal length of carry select adder.
In this figure, 16-bit Linear Carry Select Adder has block size as 4 can be created with three of these blocks and a 4 bit ripple carry adder. Since Cin is known at the beginning of computation, a carry select adder block is not needed for the first four bits. Total delay of linear carry select adder can be calculated by four full adder delays, plus three MUX delays. The disadvantages of linear carry select adders are high area usage and high delay.
Figure 2 16 Bit Linear Carry Select Adder 1.3 SQUARE ROOT CSLA
The SQRT CSLA can be implemented in different length. From previous stage of multiplexer block and two carry chains of delay can be equalized in SQRT CSLA. This adder is also called as Nonlinear CSLA.
A square-root (SQRT) CSLA to implement large bit- width adders with less delay. Increasing number of different bit CSLA is connected by a cascading structure in SQRT CSLA. To provide a parallel path for carry propagation that helps to reduce the overall adder delay in SQRT CSLA.
The disadvantages of linear carry select adder can be overcome by SQRT CSLA. The time delay of linear adder can be decreased by having one more input into each set of adders in SQRT CSLA.
In Figure 3. 16-bit SQRT Carry Select Adder having different block sizes can be created with 2,3,4,5 bits and 2 bit ripple carry adder. The total delay is two full adder delays, and four MUX delays.
Figure 316 Bit SQRT Carry Select Adder 1.4 BINARY TO EXCESS-1 CONVERTER (BEC)
BEC is used to add 1 to the input numbers. The Boolean
logic for 3-bit BEC has developed using ~NOT, &AND and
^XOR gates. It is very easy to develop higher bit size BEC architectures because it has the same basic building block of AND XOR gates for higher bits.
Figure 4 3 Bit Binary to Excess-1 Converter In Figure 4a circuit of 3 bit Binary to Excess-1 Converter has input as B0, B1 and B2, then produces an output as X0, X1 and X2.
The Boolean expression of the 3 bit BEC are shown below:
X0 = ~B0 ... (1) X1 = B0⊕ B1 ... (2) X2 = B2⊕ (B1× B0) ... (3)
In Table 1. the value of 001 is add to each 3-bit input number B and produces the 3-bit ouput number X.
BINARY [3:0] EXCESS-1 [3:0]
B2 B1 B0 X2 X1 X0
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0
Table 1 3 Bit Binary to Excess-1 Converter 1.5 DELAY AND AREA CALCULATION
The AOI (AND, OR, and INVERTER) implementation of an XOR gate is shown in Figure 5. The operations of all gates are performed in parallel and the numeric representation of each gate is indicated as delay for that gate.
The delay and area can be evaluated by considering all gates to be made up of AND, OR, and Inverter, each having
delay equal to 1 unit and area equal to unit [4]. Then add up the number of gates in the longest path of a logic block that contributes to the maximum delay.
Figure 5 Delays and Area Evaluation of an XOR Gate The area is evaluated by counting total number of AOI gates required for each logic blocks. The delay evaluation is done by performing parallel operation of XOR gate. The CSLA blocks consist of 2:1 MUX, Half Adder (HA), and Full Adder (FA) of area and delay can be evaluated and listed in Table 2
Adder Blocks Delay Area
XOR 3 5
2:1 Mux 3 4
Half Adder 3 6
Full Adder 6 13
Table 2 Delay and Area count of blocks in CSLA II.EXISTING METHOD
2.1 CONVENTIONAL SQRT CSLA USING RCA A conventional carry select adder (CSLA) is an RCA–
RCA configuration that generates a pair of sum and output carry bits corresponding to input carry (Cin= 0 and Cin = 1) and selects one out of each pair for final sum and final carry out [5].
Basically CSLA has two units:
1) Sum and Carry Generator unit (SCG) 2) Sum and Carry Selection unit (SCS)
Figure 6 Conventional SQRT CSLA Using RCA In Figure 6, the SCG unit of the conventional CSLA is composed of two n bit RCAs, where n is the adder bit-width.
The SCG unit consumes most of the logic resources of CSLA and significantly contributes to the critical path. A conventional CSLA has less Carry Propagation Delay (CPD) when compared to ripple carry adder.
2.2 LOGIC EXPRESSIONS OF THE SCG UNIT OF CONVENTIONAL CSLA
The logic operation of the n-bit RCA is performed in four stages:
1) Half Sum Generation (HSG) 2) Half Carry Generation (HCG) 3) Full Sum Generation (FSG) 4) Full Carry Generation (FCG)
Figure 7 Logic Operations of RCA
Logic expressions of RCA is given by
s00(i) = A (i) ⊕ B (i) …………. (4)
c00(i) = A (i) * B (i) …………. (5)
𝑠10(i) = s00(i) ⊕ c10(i-1) .……….. (6)
c10(i) = 𝑐00(i) + s00(i) * c10(i-1) ………… (7)
cout0 = c10(n-1) ………… (8)
s01(i) = A (i) ⊕ B (i) ………… (9)
c01(i) = A (i) * B (i) ………… (10)
𝑠11(i) = s01(i) ⊕c11(i-1) ..………. (11)
c11(i) = c01(i) + s01(i) * c11(i-1) ………… (12)
cout1 = c11(n-1) ………….. (13)
Where c10(-1) =0, c11(-1) =1, and 0 i n-1. The carry select adder achieves higher speed of operation at the cost of increased number of devices used in the circuit. This in turn increases the area and power consumed by the circuits of this type structure. The CSLA is used in many computational systems to alleviate the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum. The RCA has the lowest speed amongst all the adders because of large propagation delay. 2.3 CARRY SELECT ADDER USING BEC-1 Figure 8 CSLA using BEC-1 In Figure 8, instead of using a pair of RCA block, BEC based CSLA architecture has developed using a single ripple carry adder with Binary to Excess-1 converter, which replace the RCA block for Cin=1, in order to reduce the area and power consumption as compare to the conventional CSLA [6]. To replace n bit RCA block, it requires n+ 1bit BEC architecture. One input for mux is BEC output and another input for the mux is the RCA with Cin=0. This produces the two possible partial results in parallel and the mux is used to select either the BEC output or the direct inputs according to the control signal Cin. The logic expressions of BEC-based CSLA is given by s11(0) = 𝑠10(0) (14)
c11(0) = 𝑠10(0) (15)
𝑠11(i) = s10(i) ⊕ 𝑐11(i-1) (16)
𝑐11(i) = s10(i) * 𝑐11(i-1) (17)
cout1 = 𝑐10(n-1) ⊕𝑐11(n-1) (18)
For 0 i n-1. In Figure 8, the RCA calculates n-bit sum s01and cout1 corresponding to Cin=0. The BEC unit receives s01and cout0 from the RCA and generates (n + 1)-bit excess-1 code. From equation (4)-(6) and (14)–(18) that, in the case of the BEC-based CSLA c11depends on 𝑠10, which otherwise has no dependence on 𝑠10in the case of the conventional CSLA. It is clear that BEC structure reduces the area and power but the disadvantage is that delay is high than conventional CSLA. The advantage of this BEC logic uses lesser number of logic gates. III. PROPOSED SYSTEM 3.1 MODIFIED CARRY SELECT ADDER It has been analyzed that the architecture of conventional CSLA and BEC based CSLA have scope to reduce area. The modified CSLA design is based on the logic expressions shown in below S0 (i) = A (i) ⊕ B (i) ……….. (19)
C0 (i) = A (i) * B (i) ……….. (20)
c10 (i) = 𝑐10(i-1) * S0 (i) + C0 (i) ... (21)
for (𝑐10(0) = 0) 𝑐11 (i) = 𝑐11(i-1) * S0 (i) + C0 (i) … (22) for (𝑐11(0) = 1) C (i) = 𝑐10(i) if (Cin = 0)……….. (23)
C (i) = 𝑐11(i) if (Cin = 1)……….. (24)
Cout(0) = c (n-1) ……….. (25)
Compared to Conventional CSLA and BEC based CSLA, the modified CSLA has the logic expressions of s10 and s11 are identical except the terms c10 andc11. It has been find c10 and c11 depend on {S0, C0, Cin}, where C0 = c10= c11 . Since c10 and c11 have no dependence on s10 ands11, the logic operation of c10 and c11 can be scheduled before s10 ands11, and the select unit can select one from the set ( s10, s11) for the final sum of the CSLA.
It has been find that large amount of logic resources is used for calculating of s10 and s11 in conventional and BEC based CSLA. It is not an efficient approach to reject one sum word after the calculation. Instead of that to select one carry word from the anticipated carry words {c0 and c1} to calculate the final sum.
The selected carry word is added with the half-sum (S0) to generate the final sum (S). All these features result in an area–delay and energy-efficient design for the CSLA.
Figure 9 Modified CSLA (MCSLA)
Figure 9, consists of one HSG unit, one FSG unit, one CG unit, and one CS unit. The CG unit consist of CG0 and CG1, CG0 is carry generation unit to input carry ‗0‘ and CG1
for input carry ‗1‘.
The HSG unit receives two n-bit operands (A and B) and generate half-sum word S0 and half-carry word C0 of width n bits each. Both CG0 and CG1 receive S0 and C0 from the HSG unit and generate two n-bit full-carry words c10 and c11corresponding to input-carry ‗0‘ and ‗1‘, respectively.
The CS unit selects one final carry word from the two carry words available at its input line using the control signal Cin. It selects c10 when Cin =0; otherwise, it selectsc11. The CS unit can be implemented using an n-bit 2-to-l MUX. The final carry word C is obtained from the CS unit.
The MSB of C is sent to output as Cout, and (n−1) LSBs are XOR‘ed with (n−1) MSBs of half-sum (S0) in the FSG to obtain (n−1) MSB‘s of final-sum (S). The LSB of S0 is XOR‘ed with Cin to obtain the LSB of S.
Using this method has three advantages:
1) Calculation of s01
is avoided in the SCG unit 2) The n-bit select unit is required instead of the (n + 1) bit
3) Small output-carry delay.
Figure 10 shows that the 16 bit modified SQRT Carry Select Adder has cascaded configuration of different bit size as 2 bit RCA, 2 bit MCSLA, 3 bit MCSLA, 4 bit MCSLA, and 5 bit MCSLA.
Figure 10 16 bit Modified SQRT CSLA
In general, the 32 bit has cascaded configuration of different bit size as 2 bit RCA, 2 bit MCSLA, 3 bit MCSLA, 4 bit MCSLA, 6 bit MCSLA, 7 bit MCSLA, and 8 bit MCSLA [7].
Figure 11 shows that the 32 bit Modified CSLA has bit size as 2 bit RCA, 2 bit MCSLA, 3 bit MCSLA, 4 bit MCSLA, 5 bit MCSLA, 6 bit MCSLA, and 10 bit MCSLA.
Figure 11 32 bit Modified CSLA
In general, the 64 bit has cascaded configuration of different bit size as 2 bit RCA, 2 bit MCSLA, 3 bit MCSLA, 4 bit MCSLA, 6 bit MCSLA, 7 bit MCSLA, 8 bit MCSLA, 9 bit MCSLA, 11 bit MCSLA, and 12 bit MCSLA.
In figure 12 64 bit Modified CSLA has bit size as 2 bit RCA, 2 bit MCSLA, 3 bit MCSLA, 4 bit MCSLA, 5 bit MCSLA, 6 bit MCSLA, 10 bit MCSLA, and two 16 bit MCSLA.
Figure 12 64 bit Modified SQRT CSLA
IV.RESULTS AND DISCUSSION
The 4 bit MCSLA is simulated using Modelsim 10.0c and the simulation output is shown in Figure 13.
Figure 13 Simulation output of 4 bit Modified CSLA The 8 bit MCSLA is simulated using Modelsim 10.0c and the simulation output is shown in Figure 14
Figure 14 Simulation output of 8 bit Modified CSLA The 16 bit MCSLA is simulated using Modelsim 10.0c and the simulation output is shown in Figure 15
Figure 15 Simulation output of 16 bit Modified CSLA
The 32 bit MCSLA is simulated using Modelsim 10.0c and the simulation output is shown in Figure16.
Figure 16 Simulation output of 32 bit Modified CSLA The 64 bit MCSLA is simulated using Modelsim 10.0c and the simulation output is shown in Figure 17.
Figure 17 Simulation output of 64 bit Modified CSLA
COMPARISON OF AREA FOR CSLA BITS CONVENTIONAL
CSLA
CSLA USING BEC
MODIFIED CSLA
4 1490 1106 698
8 2142 1665 698
16 5378 4028 2770
32 11058 8812 5471
64 22326 20176 10779
COMPARISON OF POWER (nW) FOR CSLA
V.CONCLUSION
Modified CSLA has reduced all redundant logic expression of conventional CSLA and BEC based CSLA.
Carry selection operation is scheduled before calculating final sum, which is different from conventional CSLA. It can be conclude that modified CSLA require less number of gates than existing CSLA for 4-bit, 8-bit, 16- bit, 32-bit, 64- bit. Hence the Modified SQRT CSLA involves significantly less area, power and delay for 4-bit, 8-bit, 16-bit, 32-bit and 64-bit. It is verified and simulated using cadence virtuoso window. This system is used in various applications like multipliers, in digital signal processors to execute various algorithms like FFT, FIR and IIR.
REFERENCES
[1]. Mary Joseph and Renji Narayanan, ―16 Bit Carry Select Adder with Low Power and Area‖, International Journal on Recent and Innovation Trends in Computing and Communication , Volume: 2, Issue: 5.
[2]. Basant Kumar Mohanty and Sujit Kumar Patel,
―Area–Delay–Power Efficient Carry-Select Adder‖, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II, VOL.
61, NO. 6, JUNE 2014.
[3]. Shrishtikhurana and Dinesh Kumar Verma, ―SQRT CSLA with Less Delay and Reduced Area Using FPGA‖, International Journal of Research in Advent Technology, Vol.2, No.6, June 2014.
[4]. B. Ramkumar and H. M. Kittur, ―Low-power and area-efficient carry-select adder,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 2, pp. 371–375, Feb.
2012.
[5]. A. P. Thakare1 and S. Agrawal,―Design of High Efficiency Carry Select Adder Using SQRT Technique‖, International Journal of Emerging Technology and Advanced Engineering, Volume 3, Issue 7, July 2013.
[6]. M. Vidhya and R. Muthammal, ―A Novel Designing Approach for Low Power Carry Select Adder‖, International Journal of Recent Trends in Electrical &
Electronics Engg.,April. 2014.
[7]. GarimaSingh,‖Design of Low Area and Low Power Modified 32-BIT Square Root Carry Select Adder‖, International Journal of Engineering Research and General Science Volume 2, Issue 4, June-July, 2014.
ABOUT THE AUTHORS
SHEEBA A1currently working as Assistant Professor in ECE Department at Dr.Sivanthi Aditanar College of Engineering, Tiruchendur She received her ME Degree in Communication Systems From Francis Xavier Engineering College, under Anna University Chennai and her BE Degree in ECE from Dr.G U Pope College of Engineering, under Anna University Chennai.
MANGALA MARISELVI E2received her Bachelor of Engineering degree in Electronics and Communication Engineering from Dr.Sivanthi Aditanar College of Engineering under Anna University, Chennai. Currently pursuing Master of Engineering in Very Large Scale Integration (VLSI) from Dr.Sivanthi Aditanar College of Engineering under Anna University, Chennai.
ANITHA K3received her Bachelor of Engineering degree in Electronics and Communication Engineering from Dr.Sivanthi Aditanar College of Engineering under Anna University, Chennai. Currently pursuing Master of Engineering in Very Large Scale Integration (VLSI) from Dr.Sivanthi Aditanar College of Engineering under Anna University, Chennai.
BITS CONVENTIONAL CSLA
CSLA USING BEC
MODIFIED CSLA
4 64350.844 60603.225 31071.563
8 101379.769 84147.508 32746.662
16 234160.071 208511.82 126752.98
32 517306.295 494179.50 262144.83
64 1144816.201 1121068.891 510144.71
