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FIELD-EFFECT TRANSISTORS (FETs)

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Introduction

•BJTs (bipolar junction transistors) were covered in previous chapters.

•Now we will discuss the second major type of transistor, the FET (field-effect transistor).

•FETs are unipolar devices because, they operate only with one type of charge carrier.

•The two main types of FETs are

▪Junction Field-Effect Transistor (JFET)

▪Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)

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Introduction

•Recall that a BJT is a current-controlled device; that is, the base current (I

B) controls the amount of collector current (IC).

•A FET is a voltage-controlled device, where the voltage between two of the terminals (gate and source) controls the current through the device.

•A major advantage of FETs is their very high input resistance.

•Because of their nonlinear characteristics, they are generally not as widely used in amplifiers as BJTs except where very high input impedances are required.

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The Junction Field Effect Transistor

(JFET)

•The JFET (junction field-effect transistor) is a type of FET that operates with a reverse-biased pn junction to control current in a channel.

•Depending on their structure, JFETs fall into either of two categories:

n-channel

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Basic Structure of JFET

• The JFET (Junction Field Effect Transistor) is a normally ON device.

• The n-channel is connected with two leads i.e. Drain and Source

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Basic Operation of JFET

•VDD provides a drain-to-source voltage

and supplies current from drain to source.

•VGG sets the reverse-bias voltage between the gate and the source.

•The JFET is always operated with the gate-source pn junction reverse-biased.

•Reverse-biasing of the gate-source junction with a negative gate voltage

produces a depletion region along the pn junction, which extends into the n- channel and thus increases its resistance by restricting the channel width.

•The channel width and thus the channel resistance can be controlled by varying the gate voltage, thereby controlling the amount of drain current, I

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Basic Operation of JFET

•The JFET is a normally ON device.

•For the n-channel device, when the drain is positive with respect to the source and there is no gate-source voltage (VGS=0), there is current in the channel. (normally ON means ON even when VGS=0)

•When a negative gate voltage is applied to the JFET, the electric field causes the channel to narrow, which in turn causes current to decrease.

• The white areas represent the depletion region created by the reverse bias.

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JFET Symbols

Notice that the arrow on the gate points “in” for

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The JFET

•There are two types of JFETs: n-channel and p-channel.

•The symbol for an n-channel JFET is shown, along with the proper polarities of the applied dc voltages.

•The dc voltage polarities are opposite for p- channel.

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Summary

• Field-effect transistors are unipolar devices (one-charge carrier). • The three FET terminals are source, drain, and gate.

• The JFET operates with a reverse-biased pn junction (gate- to-source).

• The high input resistance of a JFET is due to the reverse- biased gate-source junction.

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JFET Characteristics and Parameters

There are three regions in

the characteristic curve for

a JFET as shown for the

case when V

GS

= 0V.

Between

A

and

B

is the

Ohmic

region

, where current and

voltage are related by Ohm’s

law.

From

B

to

C

is the

active

region

(or

constant-current

)

where current is essentially

independent of

V

DS

.

Beyond

C

is

the

breakdown

region

.

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JFET Characteristics and Parameters

•Consider the case when the gate-to-source voltage is zero (V

GS=0V).

•This is produced by shorting the gate to the source, where both are grounded.

•Consider the curve between points A and B: •As V

DD (and thus VDS) is increased from 0V, ID will increase

proportionally.

•In this area, the channel resistance is essentially constant because the depletion region is not large enough to have significant effect.

•This is called the ohmic region because VDS and ID are related by Ohm’s law.

•Consider point B on the curve:

•The curve levels off and enters the active region where ID becomes essentially constant.

•Consider the curve between points B and C:

•As VDS increases from point B to point C, the reverse-bias voltage from gate to drain (V

GD) produces a depletion region large enough to

offset the increase in V

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JFET Characteristics and Parameters

•Pinch-Off Voltage

•For VGS=0V, the value of VDS at which ID becomes essentially constant (point B on the curve) is the pinch-off voltage, VP. For a given JFET, VP has a fixed value.

•A continued increase in VDS above the pinch-off voltage produces an almost constant ID.

•This value of drain current is IDSS (Drain to Source current with gate Shorted).

•I

DSS is the maximum drain current that a specific JFET can

produce regardless of the external circuit, and it is always specified for the condition VGS=0V.

•Breakdown

Consider point C on the curve:

•Breakdown occurs when ID begins to increase very rapidly with any further increase in VDS.

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JFET Characteristics and Parameters

V

GS

Controls I

D

•As VGS is set to increasingly

more negative values by

adjusting VGG, a family of drain

characteristic curves is produced.

•ID decreases as the magnitude

of VGS is increased to larger

negative values because of the

narrowing of the channel.

•For each increase in

V

GS

, the

JFET reaches pinch-off (where

constant current begins) at

values of

V

DS

<

V

P

.

•Therefore, the amount of drain

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JFET Characteristics and Parameters

Cutoff Voltage

The value of

V

GS

that makes

I

D

≈0 is the cutoff voltage,

V

GS(off)

.

The JFET must be operated between

V

GS

=0

and

V

GS

(off)

.

For this range of gate-to-source voltages (

V

GS

),

I

D

will

vary

from

a

maximum

of

I

DSS

to

a

minimum of almost zero.

For an

n

-channel JFET, the more negative

V

GS

is, the

smaller

I

D

becomes in the active region.

When

V

GS

has a sufficiently large negative value

(=

V

GS(off)

),

I

D

is reduced to zero.

This cutoff effect is caused by the widening of the

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JFET Biasing

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References

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