Bore Gowda H. B. and Aravind R. ijesird, Vol. III, Issue VI, December 2016/ 347
DESIGN AND SYNTHESIS OF DIGITAL FIR LOW-PASS FILTER BASED ON KAISER
WINDOW FUNCTION
Bore Gowda H.B.1, Aravind R.2
1,2 Assistant Professor, Dept of ECE, GSSSIETW, Mysuru
1 [email protected], 2 [email protected]
Abstract-This paper describes an approach to the implementation of digital filter algorithms based on field programmable gate arrays (FPGAs).The advantages of the FPGA approach to digital filter implementation include higher sampling rates than are available from traditional DSP chips, lower costs than an ASIC for moderate volume applications, and more flexibility than the alternate approaches. In this paper, digital FIR filter has been designed by using Kaiser windows.
This technique is simple conceptually and computationally. The design of the filter is formulated as a problem of optimizing, which is the modified zeroth-order Bessel function of the first kind. Besides this the adjustable parameter, has been selected so as to optimise the main lobe width. On the other hand, because in Kaiser designs the stop band attenuation is determined by the window, direct control over the stop band attenuation can be achieved. The FIR filter is implemented in Spartan-III-xc3s200- 4tq144 FPGA and simulated with the help of Xilinx ISE (Integrated Software Environment). Software WEBPACK project navigator 10.1 was used for synthesizing and simulation the code. For an N order filter the number of shift register and adders required is N and the number of multipliers required is M+1. These filters can work in real time.
Keywords- FPGA; Kaiser window; DSP chip; ASIC
I INTRODUCTION
The most common approaches to the implementation of digital filtering algorithms are general purpose digital signal processing chips for audio applications, or special purpose digital filtering chips and application-specific integrated circuits (ASICs) for higher rates. FIR (Finite Impulse Response) digital filters having the advantage of high stability and easily obtaining linear phase than IIR (Infinite Impulse Response) digital filters were widely used in signal detection and processing fields. As the increasing of the amount of signal processing, real-time requirements have become more sophisticated ,the original means using DSP (Digital Signal Processing) processor in many occasions can no longer meet the requirements. The FPGA (Field Programmable Gate Array) which based on look-up table structure
and had the hardware characteristics of parallel execution, shows more excellent features than the DSP in the high-capacity data processing[1,2]. How to design a high-speed FIR digital filter implemented on FPGA has become a hot research field in signal processing in recent years. In general, FIR filters implemented on FPGA are used to Achieve by encoding the underlying hardware description language, its development efficiency of this method is very low. Liu Xiongfei, etc. [3] first using the DSP Builder tool to design adaptive filter and has achieved good results. On the basis of Liu Xiongfei’s research, a new system modeling method for designing the FIR filter based on DSP Builder was proposed in this paper, through this way, the development efficiency and filter’s performance has been greatly improved.
II. FIR FILTER DESIGN BASED ON KAISER WINDOW FUNCTION
Direct-type FIR filter expression was as follows:
Where x (n) is the input sequence, h (i) is the filter’s coefficients, M is the filter’s tap, and y (n) is the filter’s output sequence. It can be seen that a FIR filter was mainly composed by multipliers, adders and delay units. As we all know, in an ideal filter, frequency response function h (n) is an infinite and non-causal sequence, but in an actual designed filter, h (n) must be finite[6]. So in the practical application of filter designing, we usually use a
Bore Gowda H. B. and Aravind R. ijesird, Vol. III, Issue VI, December 2016/ 348 finite length window function sequence ω (n) to
intercept, that is, to approximate the infinite as follows:
Usually, window functions which used most were rectangular window, Bartlett window, Hamming window, Hann window, Blackman window, Kaiser window and so on. Kaiser window provides a variable transition bandwidth. In this paper, Kaiser Window function was selected to design FIR filter. Its window function expressed as follow:
Where I0 [•] was the deformation of the first kind zero-order Bessel function, the shape parameter β which depending on the filter taps M was used to adjust the main lobe width and side lobe attenuation, choosing M can produce a variety of transition band and the optimal stop band attenuation[7].
III. FILTER COEFFICIENTS CALCULATION AND ITS AMPLITUDE-FREQUENCY
CHARACTERISTICS
Design specifications: designing a low-pass FIR filter with a cutoff frequency of 100 KHz and a sampling frequency of 1MHz based on Kaiser window function. Using matlab’s fdatool kit, the filter parameters meeting the above requirements were calculated out.
Figure 1. The amplitude-frequency characteristic curve of the designed filter
Figure 1 is the amplitude-frequency characteristic curve of the designed FIR filter. It can be seen that at 100 KHz cutoff frequency, the gain is about -6dB, then decreases rapidly to less than - 20dB. Filter’s performances meet the requirements.
Table 1 is the filter’s coefficients, from the table, we can see that to meet the performance requirements, the designed filter must be not less than 16-tap and its coefficients were symmetric and it was a linear phase filter.
Table 1: Coefficients of the designed filter
Bore Gowda H. B. and Aravind R. ijesird, Vol. III, Issue VI, December 2016/ 349 IV. FIR FILTER MODELING BASED ON DSP
BUILDER
Using the new FPGA development software DSP Builder developed by Altera company, an 16- tap direct form FIR filter model was built, it was shown as Figure 2.The model mainly was composed of 15 Z-1 delay units, 16 product multipliers, 16 constant filter coefficient modules and a parallel adder. In addition, a 50 KHz square wave was used as input signal, a virtual oscilloscope and FFT spectrum scope analyzer were used to measure the time domain and frequency domain waveform of input and output signals.
Figure 2. 16-tap FIR filter model
V. SIMULATIONS AND ANALYSIS Figure 3 is the time domain simulation waveforms of the designed FIR low-pass filter model in simulink. Figure 4 and Figure 5 are the frequency spectrums of the filter’s input and output signal. As shown in the figures, after passed through the designed low-pass filter with a cut-off frequency of 100 KHz, 50 KHz square wave left only the fundamental wave of 50 KHz and direct- current component, almost all the higher harmonics were filtered out. After this verification, the model was converted into RTL (Register Transfer Level)
Bore Gowda H. B. and Aravind R. ijesird, Vol. III, Issue VI, December 2016/ 350 VHDL language procedure by running signal
compiler tool. Then the RTL VHDL procedure was simulated on Modelsim-altera software, simulation results was shown in Figure 6, the filtering effect was very good. On this basis, the procedure was compiled, synthesized and fitted on Quartus II software. Finally, a FIR low-pass filter with a highest frequency response of 61.71 MHz was implemented on Spartan-III-xc3s200-4tq144 FPGA and simulated with the help of Xilinx ISE (Integrated Software Environment). FPGA resource usage: logicalunits 2,262 / 33,216 (7%), dedicated logic registers 717/33, 216 (2%), pins 78/475 (16%), embedded multipliers 70/70 (100%).
Figure 3. The FIR low-pass filter model simulation waveforms on Simulink
Figure 4. The frequency spectrum of filter input signal
Figure 5. The frequency spectrum of filter output signal
Figure 6. RTL timing simulation waveform of the filter
VI. CONCLUSIONS
This paper has described an approach to the implementation of digital filter algorithms based on field programmable gate arrays (FPGAs). General purpose DSP implementations often lack the performance necessary for moderate sampling rates, and ASIC approaches are limited in flexibility and may not be cost effective for many applications.
Our examples of FIR and IIR filter implementations illustrate that the FPGA approach is both flexible and provides performance comparable or superior to traditional approaches. Because of the programmability of this technology, the examples in this paper can be extended to provide a variety of other high performance FIR and IIR filter realizations.
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