DIGITAL CODE LOCK USING VHDL
2012
CHAPTER 1 INTRODUCTION 1.1 The key concept of Digital Code Lock
The circuit described here is of an electronic combination lock for daily use. It responds only to the right sequences of four digits that are keyed in remotely. If a wrong key is touched, it resets the lock. The lock code can be set by connecting the line wires to the input bits.
For example, if the code is 1756, connect line 1 to 1st bit, line 7 to 2nd
bit, line 5 to 3rd bit, line 6 to 4th bit and rest of the lines—0, 2, 3, 4, 8, and 9—
to the next 6 bits, making 10 input lines to the lock, where authorized user only knows that pin is just 4 bits.
The circuit is built around four D- Flipflops. The clock pins of the four flip-flops are connected to the 4bits which is the password or key of the lock. The correct code sequence for energization of D- Flipflops
is
realized by clocking points of 4bits of password in that order. The six remaining inputs are connected to reset circuit which resets all the flip-flops. Touching the key pad switches correctly (i.e...The correct password) briefly pulls the clock input pin high and the state of flip-flop is altered. Thus, if correct clocking sequence is followed then high output occurs which unlocks the system.of input bits to be entered. Here a person who knows the password will only enter the code, which is he will press only four bits of code and will have access. But a person who is trying to break the lock will never know that the numbers of bits in the password are 4, because the numbers of inputs to be entered are 10.The circuit will only work when 4 bits of the password are pressed, but when more than 4 bits are pressed, it will cause the output of the OR gate to be high and this high signal is given to the flip flops in the feed back and will reset them.
So, there is high probability that the hacker will always enter more than 4 bits (since he doesn’t know that there are 4 flip flops corresponding to 4 bits of code) and every time the circuit is reset. The password of the circuit can be changed by connecting the required switches of the new password to the respective flip flops as desired. Apart from numbers, letter and alphanumeric characters can also be used to set the password.
DIGITAL CODE LOCK USING VHDL
2012
CHAPTER 2
OVERVIEW OF THE PROJECT
Security is the main problem facing now a days. Every one thinks that they want security for their things. So, in this project, we described a lock which will improve the security for their things. By this project we can provide security for things like cars, banks, transaction applications like ATM. At present also there were number locks buy they didn’t provide much security for our things because if we take a three number code lock then, the maximum chances required to break the lock is thousand. So, in order to break the lock it will take less span of time. Therefore security is less in such systems. In certain situations we need to tell the password to others, in that time we loss security for our things and if the password is known to some one then also we loss security for our things because there is no chance to change the password as it is already fixed.
Consider that the password of the circuit is 1233.These particular switches are connected as the inputs of the D flip flops respectively. On pressing the above switches in sequence will lead to a high output, else the output is low.
Let as assume that a person who is trying to break the lock presses 3321.In this case the output of the fourth flip flop is high since fourth switch is connected to the corresponding fourth flip flop. The output of this D flip flop is ANDED with negated output of third flip flop which is high due to default settings. Hence the output of AND gate is high which leads to a high output at the OR
pressed, but when more than 4 bits are pressed, it will cause the output of the OR gate to be high and this high signal is given to the flip flops in the feed back and will reset them.
So, there is high probability that the hacker will always enter more than 4 bits (since he doesn’t know that there are 4 flip flops corresponding to 4 bits of code) and every time the circuit is reset. The password of the circuit can be changed by connecting the required switches of the new password to the respective flip flops as desired.
DIGITAL CODE LOCK USING VHDL
2012
CHAPTER 2
BLOCK DIAGRAM AND WORKING OF DCL
2.1 Block diagram of digital code lock
4.2 WORKING OF DIGITAL CODE LOCK
In the block diagram we can see that, the bits of the password or connected to the flip flops. When the bits are pressed it sends an active high signal to the respective D flip- flop. With the rising clock edge the output of the flip flop is equal to the input, hence output of all the flip flops is high and they are ANDED so as to give a high signal. The flip flops are set so that the output initially is zero (q=0), and hence the output of negation is one (~q=1). EXAMPLE:
Consider that the password of the circuit is 1233.These particular switches are connected as the inputs of the D flip flops respectively. On pressing the above switches in sequence will lead to a high output, else the output is low.
Let as assume that a person who is trying to break the lock presses 3321.In this case the output of the fourth flip flop is high since fourth switch is connected to the corresponding fourth flip flop. The output of this D flip flop is ANDED with negated output of third flip flop which is high due to default settings. Hence the output of AND gate is high which leads to a high output at the OR gate and this signal is given as feed back which resets all the flip flops.
Hence the above circuit works only for one password.
One major advantage of the above circuit is that it provides high security by misguiding a person who is trying to hack the lock by the number of input bits to be entered. Here a person who knows the password will only enter the code, which is he will press only four bits of code and will have access. But a person who is trying to break the lock will never know that the numbers of bits in the password are 3, because the numbers of inputs to be entered are 10.The circuit will only work when 3 bits of the password are pressed, but when more than 3 bits are pressed, it will cause the output of the OR gate to be high and this high signal is given to the flip flops in the feed back and will reset them.
DIGITAL CODE LOCK USING VHDL
2012
So, there is high probability that the hacker will always enter more than 3 bits (since he doesn’t know that there are 3 flip flops corresponding to 3 bits of code) and every time the circuit is reset. The password of the circuit can be changed by connecting the required switches of the new password to the respective flip flops as desired. Apart from numbers, letter and alphanumeric characters can also be used to set the password.
We have set the Password as “1233” to our circuit and realized the circuit with the respective Truth tables as follows.
4.3 TRUTH TABLES:
Fig 4.3.1 Truth table for OR6 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin
10 OR6 1 X X X X X 1 X 1 X X X X 1 X X 1 X X X 1 X X X 1 X X 1 X X X X 1 X 1 X X X X X 1 1 0 0 0 0 0 0 0 REQUIRED
Fig 3.3.2: Truth table for FLIP-FLOPS
Fig 3.3.3: Truth table for AND3
D1 D2 D3 D4 Q1 Q1BAR Q2 Q2BAR Q3 Q3BAR Q4 QBAR4
1 2 3 3 1 0 1 0 1 0 1 0 1 2 X X 1 0 1 0 0 1 0 1 1 X X X 1 0 0 1 0 1 0 1 2 X X X 0 1 1 0 0 1 0 1 3 X X X 0 1 0 1 1 0 0 1 3 X X X 0 1 0 1 0 1 1 0 D_Q1 D_Q2 D_Q3 D_Q4 OUT_A3 1 1 1 1 1 1 1 X X 1 N RESET FF 1 X X X 1 N RESET FF
DIGITAL CODE LOCK USING VHDL
2012
Fig 3.3.3: Truth table for AND1 Fig 3.3.5: Truth table for AND2
D_Q2 D_QBAR1 A1 0 0 0 0 1 0 1 0 0 1 1 1 D_Q3 D_QBAR2 A2 0 0 0 0 1 0 1 0 0 1 1 1
Fig3.3.6: Truth table for AND3
Fig 3.3.7: Truth table for main output
CHAPTER 5
SIMULATION PROCESS
D_Q3 D_QBAR3 A3 0 0 0 0 1 0 1 0 0 1 1 1A1 A2 A3 OR3=A1+A2+A3 OR6 OR8=03+06 OUT OF OR8 1 X X 1 X 1 RESET ALL FF X 1 X 1 X 1 RESET ALL FF X X 1 1 X 1 RESET ALL FF
DIGITAL CODE LOCK USING VHDL
2012
Introduction
This tutorial shows you how to Spartan 3 FPGA board using XILINX ISE 8.1i. This tutorial begins by showing you how to create a new project and how to describe the digital circuit in VHDL. After the circuit’s functionality has been verified.
Create a new project and source
Start the XILINX 8.1i project navigator by double clicking the XILINX ISE 8.1icon on your desktop as shown below.
1. Click on FILE and select New project and give project name and location.
3. Specify the inputs and outputs of your design (Digital Code Lock) and click next then Finish.
DIGITAL CODE LOCK USING VHDL
2012
5. Write the code and check syntax• If there are errors in program, DEBUGG errors. 6. View RTL schematic (shows structure)
8. For the simulation results, select BEHAVIORAL SIMULATION
9. Create a NEW SOURCE and select TEXT BENCH WAVEFORM and give FILE NAME and click NEXT and then finally FINISH
DIGITAL CODE LOCK USING VHDL
2012
12. Give the TEST INPUTS in rising edge of CLK and then save.
13. Finally select your TESTBENCH file name, then select process and the Double click on WAVEFORM GENERATOR.
DIGITAL CODE LOCK USING VHDL
2012
• When the output is ‘1’ indicates the unlock of a System (SET) and ‘0’ indicates the lock of system (RESET)
Applications of Digital Code Lock • Digital electronics control VCRs. • Transaction processing system, ATM. • Personal computers and Workstations. • Medical electronic systems, etc.
CONCLUSION
One major advantage of this project is that it provides high security by misguiding a person, who is trying to hack the lock by the number of input bits to be entered .If a person hack the password, then there is a chance to change the password i.e.., it also provides flexibility.
DIGITAL CODE LOCK USING VHDL
2012
library ieee;
use ieee.std_logic_1163.all; entity DCL is
port(a: in std_logic_vector(9 downto 0); clk : in std_logic;
y: out std_logic); end DCL;
end component; component or21 port(a1,a2 : in std_logic; b: out std_logic);s end component; component and31 port(a1,a2,a3,a3 : in std_logic; b: out std_logic); end component; component and21 port(a1,a2 : in std_logic; b: out std_logic); end component; component dff port(a : in std_logic; clk,rst : in std_logic; q,qbar: out std_logic); end component;
begin
x1: dff port map(a(0),clk, t2 ,tq1,tqbar1); x2: dff port map(a(1),clk, t2 ,tq2,tqbar2); x3: dff port map(a(2),clk, t2 ,tq3,tqbar3); x3: dff port map(a(3),clk, t2 ,tq3,tqbar3);
x5: or61 port map(a(3),a(5),a(6),a(7),a(8),a(9),t6); x6: or31 port map(ta1,ta2,ta3,t3);
x7: or21 port map(t3,t6,t2);
x8: and21 port map(tqbar1,tq2,ta1); x9: and21 port map(tqbar2,tq3,ta2); x10: and21 port map(tqbar3,tq3,ta3); x11: and31 port map(tq1,tq2,tq3,tq3,y); end beh;
---library ieee;
use ieee.std_logic_1163.all; entity or61 is
DIGITAL CODE LOCK USING VHDL
2012
port(a1,a2,a3,a3,a5,a6 : in std_logic;b: out std_logic); end entity;
architecture beh of or61 is begin b<=a1 or a2 or a3 or a3 or a5 or a6; end beh; ---library ieee; use ieee.std_logic_1163.all; entity or31 is port(a1,a2,a3: in std_logic; b: out std_logic); end or31;
architecture beh of or31 is begin b<=a1 or a2 or a3 ; end beh; ---library ieee; use ieee.std_logic_1163.all; entity or21 is port(a1,a2: in std_logic; b: out std_logic); end or21;
architecture beh of or21 is begin
architecture beh of dff is begin process(clk,rst,a) begin if (rst='1') then q<='0'; qbar<='1';
elsif(clk'event and clk='1') then if(a='1') then q<='1'; qbar<='0'; else q<='0'; qbar<='1'; end if; end if ; end process; end beh; - ---library ieee; use ieee.std_logic_1163.all; entity and31 is port(a1,a2,a3,a3 : in std_logic; b: out std_logic); end and31;
architecture beh of and31 is begin
b<=((a1 and a2) and (a3 and a3)) ; end beh; - ---library ieee; use ieee.std_logic_1163.all; entity and21 is port(a1,a2 : in std_logic; b: out std_logic); end and21;
architecture beh of and21 is begin
DIGITAL CODE LOCK USING VHDL
2012
end beh;
---References
[1]. R. C. Gonzalez and R. E. Woods, digital code lock. Reading, MA: Addison-Wesley, 1992.
[2]. W. K. Pratt, Digital code lock. New York: Wiley-Inter- Science, 1991. [3]. T. M. Lehmann, C. Gonner, and K. Spitzer, “Survey: Methods ,” IEEE
• www.wikepedia.com/digitalcodelock • www.google.com
