Corporate Presentation March 2014

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Corporate Presentation

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The following presentation, other than statements of historical fact, may include certain “forward-looking statements” within the meaning of the United States Private Litigation Reform Act of 1995 and applicable Canadian securities laws. These forward looking statements are made under the “Safe Harbor” provisions of the aforesaid act and laws. All statements regarding future plans and objectives are forward-looking statements. Words such as “expect”, “anticipate”, “estimate”, “future plans”, “may”, “will”, ”should”, “intend”, “believe”, “opportunities”, and other similar expressions are forward-looking statements. Forward-looking statements are subject to risks, uncertainties, assumptions and are not guarantees of future results, but rather reflect current views with respect to future events.

Important factors that could cause actual results to differ materially from those expressed or implied in the forward looking The following presentation, other than statements of historical fact, may include certain “forward-looking statements” within the meaning of the United States Private Litigation Reform Act of 1995 and applicable Canadian securities laws. These forward looking statements are made under the “Safe Harbor” provisions of the aforesaid act and laws. All statements regarding future plans and objectives are forward-looking statements. Words such as “expect”, “anticipate”, “estimate”, “future plans”, “may”, “will”, ”should”, “intend”, “believe”, “opportunities”, and other similar expressions are forward-looking statements. Forward-looking statements are subject to risks, uncertainties, assumptions and are not guarantees of future results, but rather reflect current views with respect to future events.

Important factors that could cause actual results to differ materially from those expressed or implied in the forward looking

Safe Harbor

statements include risks and factors disclosed under the heading “Risk Factors” in the public documents filed from time to time with the System for Electronic Document Analysis and Retrieval (“SEDAR”).

Readers should not place undue reliance on any forward-looking statements. We disclaim any obligation to update or revise any forward looking statements, except as required by law to reflect any change in expectations, events, conditions or circumstances on which any of the forward looking statements are based, or that may affect the likelihood that actual results will differ from those set forth in the forward-looking statements.

statements include risks and factors disclosed under the heading “Risk Factors” in the public documents filed from time to time with the System for Electronic Document Analysis and Retrieval (“SEDAR”).

Readers should not place undue reliance on any forward-looking statements. We disclaim any obligation to update or revise any forward looking statements, except as required by law to reflect any change in expectations, events, conditions or circumstances on which any of the forward looking statements are based, or that may affect the likelihood that actual results will differ from those set forth in the forward-looking statements.

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POET Technologies Inc. is a fabless designer of the POET

platform, a best of breed, leap forward next generation compound semiconductor.

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The POET platform builds into it monolithic fabrication of integrated circuit devices that contain both electronic and optical elements on a single semiconductor wafer.

Overview

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With head office in Toronto, Ontario, Canada, and operations in Storrs, CT, the Company’s operates in two segments, designing III-V semiconductor devices for military, industrial and commercial applications, including: infrared sensors, mobile and wearable devices, computer servers, storage arrays, imaging equipment, and networking equipment.

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The Company's common shares trade on the TSX Venture Exchange under the symbol "PTK" and on the OTCQX under the symbol "POETF". For more information please visit our websites at

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Technology Development (University of Connecticut, Storrs, CT 1994 – Present)

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Lab facility and infrastructure design/build 1994-1997

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Completion of POET concept to include p-channel devices 1997

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Third party SBIR funding 1994-2000 (10 Phase I’s , 1 Phase II) equipment build up

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Founded OPEL Technologies (now POET Technologies) in 2000, first SBIR win 2001

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First investor funding $250K to fast track Phase I SBIR start team build

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Continued OPEL SBIR funding 2000-2006 to acquire equipment and team (expert team consisting of PhDs and highly experienced semiconductor process experts)

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Technology Development (University of Connecticut, Storrs, CT 1994 – Present)

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Lab facility and infrastructure design/build 1994-1997

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Completion of POET concept to include p-channel devices 1997

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Third party SBIR funding 1994-2000 (10 Phase I’s , 1 Phase II) equipment build up

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Founded OPEL Technologies (now POET Technologies) in 2000, first SBIR win 2001

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First investor funding $250K to fast track Phase I SBIR start team build

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Continued OPEL SBIR funding 2000-2006 to acquire equipment and team (expert team consisting of PhDs and highly experienced semiconductor process experts)

• Development Background

PhDs and highly experienced semiconductor process experts)

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ODIS formation following Canadian ownership to enable SBIR funding 2006-2012

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Patent portfolio build up from 2001–2013

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Partial OPEL funding 2012-2013

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Technology Development (Bell Labs, Holmdel, NJ 1986-1994)

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Air force launched major funding initiative for OE technology development

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HFET concept in 1986 (demo 1987), BicFET laser (demo 1988)

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DOES (thyristor) laser (demo 1988)

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Technology platform established by 1992 (n-channel only)

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Technology Background and History (Bell Labs, Murray Hill, NJ 1979 - 1986)

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Starting at Bell Labs in MH-NJ in 1980-1985 in Si device lab (Lepselter/Smith) new BicFET device concept development with J.G. Simmons - BicFET patent and publication 1985

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Forced relocation from Si device development to III-V device research lab PhDs and highly experienced semiconductor process experts)

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ODIS formation following Canadian ownership to enable SBIR funding 2006-2012

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Patent portfolio build up from 2001–2013

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Partial OPEL funding 2012-2013

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Technology Development (Bell Labs, Holmdel, NJ 1986-1994)

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Air force launched major funding initiative for OE technology development

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HFET concept in 1986 (demo 1987), BicFET laser (demo 1988)

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DOES (thyristor) laser (demo 1988)

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Technology platform established by 1992 (n-channel only)

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Technology Background and History (Bell Labs, Murray Hill, NJ 1979 - 1986)

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Starting at Bell Labs in MH-NJ in 1980-1985 in Si device lab (Lepselter/Smith) new BicFET device concept development with J.G. Simmons - BicFET patent and publication 1985

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Management

Peter Copetti

Executive Chairman and CEO

Peter has over 25 years of capital markets and management experience in key leadership roles. He has been the chief architect and strategist of the transformation at POET Technologies, since joining the company in June 2012. Mr. Copetti was personally responsible for the restructuring of both secured and unsecured debt, negotiated new equity infusion into the company, and re-focused the company on its original technical vision of monolithic optoelectronic integration, leading to POET's resurgence as a leading platform innovator in the semiconductor industry. Peter is the Chairman of the Special Strategic Committee which has been mandated to look at all options for monetizing POET’s IP assets in addition to maximizing shareholder value.

Leon M. Pierhal

President,and Director

Mr. Pierhal has over forty years of management experience in semiconductor, telecommunications and computing technology development companies such as Amdahl Corporation, Intel Corporation, Masstor Systems Corporation, and Jupiter Technology. As a senior

management executive with broad international experience, Mr. Pierhal has had direct responsibility for P&L, sales and marketing, and corporate development for several major companies requiring strategic expertise.

Dr. Geoffrey Taylor

Chief Scientist

Dr. Taylor has a B.Sc, Electrical Engineering from Queens University, an M.A.Sc, Electrical Engineering from the University of Toronto, and a Ph.D., Electrical Engineering from the University of Toronto. Dr. Taylor has been involved with the Institute of Electrical and Electronics Engineers, the Optical Society of America, Lasers and Electro-Optics Society, and the International Society for Optical Engineering. He Engineers, the Optical Society of America, Lasers and Electro-Optics Society, and the International Society for Optical Engineering. He conducts his research out of the University of Connecticut and has been working on the POET platform for over a decade. He is a highly regarded expert in the fields of Optics and Electronics.

Stephane Gagnon

Senior Vice President, Operations

Stephane Gagnon has over 20 years of experience in the semiconductor, telecommunication and processor industry. His last role was Senior Director of Product Management for IDT - Integrated Device Technology where he drove business strategy for the RapidIO® switching product line with primary responsibilities that included strategy and product marketing, business development and management of international customer and partner relationships. Stephane led the charge in achieving 100% market share in the Wireless 4G Base station business. Stephane is Senior VP of Operations with the mandate to help monetize POET and manage POET’s overall operations.

Lee Shepherd

Vice President, Technology

Mr. Shepherd has a Bachelor of Science (Honors) in Applied Physics from Carleton University. He has 27 years of experience in business, technical, and military leadership roles. He has spent the last 18 years in the Telecommunications/Information Technology industry serving in technical, management, architecture, and entrepreneurial roles of ever-increasing scope and responsibility. He is Founder and Chief Executive Officer of IT Millwrights Corporation; previously Founder and Chief Technology Officer of Neterion, and Designer, Team Leader & Architect with Bell-Northern Research and Nortel.

Mark Benadiba

Vice Chairman

Mr. Benadiba is currently a Director and former Executive Vice-President, North American Operations of Cott Corporation (TSX: “BCB” / NYSE: “COT”). He was a founding senior executive in the start-up and initial expansion of Cott Corporation from a $20 million family business to a multi-billion dollar, multi-national public company. Mr. Benadiba has a proven track record in attaining private and public corporate financial objectives while consistently creating positive shareholder value including extensive experience in mergers, acquisitions, divestitures and strategic alliances. Upon joining the Cott Corporation board, Mark helped to lead the turn-around of the company in 2008, during which the Cott Corporation market value increased by more than 10x over an eight-month period

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Our Revolutionary

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What Does “POET” Mean? What Does “PET” Mean?

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“Planar Opto-Electronic Technology” and “Planar Electronic Technology”

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What is POET?

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POET is a revolutionary Gallium Arsenide (GaAs) process used to build electrical, optical, and electro-optical integrated circuits

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Supports a full range of electrical and optical active and passive circuit components

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Very high performance versus existing silicon (up to 100x faster)

• POET/PET Description

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Very low power consumption versus existing silicon (up to 95% less)

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Much more versatile than legacy compound semiconductor processes (GaAs, InP, others)

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Can be manufactured using existing CMOS chip making equipment

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Fully compatible with existing semiconductor design and manufacturing flows

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Will allow unprecedented integration into a single chip of functions that take entire chipsets today for large component cost reduction, and (particularly for optics) tremendous (e.g. 80%) reduction in assembly and test costs

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What is PET?

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PET is the electrical subset of the full POET process

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Can support CMOS, Bi-CMOS, and Bipolar device fabrication

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Offers lower cost, simpler process/fab options for applications that don’t require optical feature set

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POET’s benefits are analogous to the benefits of the first silicon integrated circuits

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Eliminating connectors, solder joints, assembly and multiple packaging steps

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Decreases size, cost, complexity and power

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Increased performance and reliability

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Creates a path for future improvements and scaling

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Board-to-board, chip-to-chip optics with low-cost integrated transceivers

Technical Advantages of

POET

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Board-to-board, chip-to-chip optics with low-cost integrated transceivers

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Substantial increase in chip I/O bandwidth with reduced power using integrated wavelength-division multiplexing

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A higher speed and lower power complementary metal-oxide semiconductor (CMOS) with

integrated serializer/deserializer & clock data recovery (SERDES & CDR)

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Novel high-density universal memory, Optical RF generation, RF photonic filtering,

Optoelectronic low-jitter clock generation and on-chip optical distribution, OE computing and new architectures based on O&E combinations (e.g. quantum computing)

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POET Technologies partners with an international defense services company that is a global leader in military electronic systems design, development, manufacturing and integration

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Funded by AFRL, POET entered into a contract with 3rd party partner in 2008 with the intent of replicating a specific POET device in a 3rd _{party MIL Spec. environment}

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The 3rd party partner has world-class GaAs research facilities and has numerous PhD

3 rd

_{Party Independent}

Validation of POET

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The 3rd party partner has world-class GaAs research facilities and has numerous PhD researchers working on the continued development of POET

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POET’s partnership has successfully reproduced the POET technology as published, by producing and testing the critical electrical elements of POET Platform sub-process steps for transistors

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Why POET Is Valuable?

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• Electronics manufacturers strive to build smarter, faster, more efficient, and cheaper devices on a continuous basis

• Semiconductor performance has historically improved at a logarithmic rate because transistors (the building blocks of semiconductors) have shrunk in size, allowing more transistors to be packed into a

semiconductor chip

• Intel’s Gordon Moore captured this trend with Moore’s Law – the idea that the number of transistors in a chip doubles every 1.5 to 2 years, thus increasing capabilities of electronic equipment

• Electronics manufacturers strive to build smarter, faster, more efficient, and cheaper devices on a continuous basis

• Semiconductor performance has historically improved at a logarithmic rate because transistors (the building blocks of semiconductors) have shrunk in size, allowing more transistors to be packed into a

semiconductor chip

• Intel’s Gordon Moore captured this trend with Moore’s Law – the idea that the number of transistors in a chip doubles every 1.5 to 2 years, thus increasing capabilities of electronic equipment

Moore’s Law and the Future

of Semiconductors

thus increasing capabilities of electronic equipment

• As transistors become smaller, the cost of reducing size / increasing speed becomes more expensive and eventually uneconomical

• Recently developed 3D silicon semiconductors stacking multiple chips and other silicon high-performance compound devices are very

expensive to make and only offer moderate improvements over incumbent chips

• By integrating optics and electronics onto one monolithic chip, semiconductor devices using the POET process can achieve

performance gains akin to Moore’s Law that have not been possible in the semiconductor world to date. POET allows for performance

improvements that are an order of magnitude greater than silicon devices at a fraction of the cost

thus increasing capabilities of electronic equipment

• As transistors become smaller, the cost of reducing size / increasing speed becomes more expensive and eventually uneconomical

• Recently developed 3D silicon semiconductors stacking multiple chips and other silicon high-performance compound devices are very

expensive to make and only offer moderate improvements over incumbent chips

• By integrating optics and electronics onto one monolithic chip, semiconductor devices using the POET process can achieve

performance gains akin to Moore’s Law that have not been possible in the semiconductor world to date. POET allows for performance

improvements that are an order of magnitude greater than silicon devices at a fraction of the cost

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CMOS Silicon Evolution Is Ending

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Moore’s Law era 1960-2015?

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CPU/GPU execution unit speeds haven’t improved in over 10 years

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Industry looking for new technology path

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Packaging Techniques Have Not Improved OE Transceiver Cost

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Various hybrid integration techniques like 2.5/3 D packaging, silicon photonics have not led to improved Opto-Electronic Transceiver costs

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Single-chip transceivers needed for fiber to fully replace copper for system

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CMOS Silicon Evolution Is Ending

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Moore’s Law era 1960-2015?

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CPU/GPU execution unit speeds haven’t improved in over 10 years

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Industry looking for new technology path

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Packaging Techniques Have Not Improved OE Transceiver Cost

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Various hybrid integration techniques like 2.5/3 D packaging, silicon photonics have not led to improved Opto-Electronic Transceiver costs

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Single-chip transceivers needed for fiber to fully replace copper for system

Ready At The Right Time

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Single-chip transceivers needed for fiber to fully replace copper for system interconnect applications

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Copper Cable Era For System Interconnect Is Ending

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1 Gigabit Ethernet system interconnect was and is mostly copper-based

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10 Gigabit Ethernet system interconnect was and is almost entirely fiber-based

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Optical Systems Need More Lithography, Less Mechanical Assembly

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Many optical systems that need aligned arrays of sensors and/or lasers cannot be built today due to mechanical assembly cost constraints

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POET offers this alignment capability by means of lithography, dramatically lowering the cost of these products (IR sensors, holographic displays, etc.)

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Single-chip transceivers needed for fiber to fully replace copper for system interconnect applications

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Copper Cable Era For System Interconnect Is Ending

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1 Gigabit Ethernet system interconnect was and is mostly copper-based

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10 Gigabit Ethernet system interconnect was and is almost entirely fiber-based

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Optical Systems Need More Lithography, Less Mechanical Assembly

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Many optical systems that need aligned arrays of sensors and/or lasers cannot be built today due to mechanical assembly cost constraints

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POET offers this alignment capability by means of lithography, dramatically lowering the cost of these products (IR sensors, holographic displays, etc.)

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POET’s technology can surpass speed limits of widely used CMOS silicon chips and is much better positioned for stacking multiple chips to increase performance

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A functional POET device may reduce the power consumption of laptops, tablets, smartphones, servers, and/or other electronic devices by 80%

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Leads to drastic reduction in device size and battery power

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POET’s technology can surpass speed limits of widely used CMOS silicon chips and is much better positioned for stacking multiple chips to increase performance

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A functional POET device may reduce the power consumption of laptops, tablets, smartphones, servers, and/or other electronic devices by 80%

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Leads to drastic reduction in device size and battery power

Applications

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Leads to drastic reduction in device size and battery power consumption

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Power reduction in commercial-scale server farms represents tremendous cost savings to companies like IBM, Google and Intel

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In November 2011, Hewlett Packard announced that it is working with numerous chip manufacturers to create

ultra-efficient, low-energy servers aimed at companies running large-scale remote computing operations such as Twitter and

Facebook

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POET can also produce an infra-red sensor for use in air, sea, ground, and space with sensitivity that is an order of magnitude higher than existing technology

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Leads to drastic reduction in device size and battery power consumption

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Power reduction in commercial-scale server farms represents tremendous cost savings to companies like IBM, Google and Intel

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In November 2011, Hewlett Packard announced that it is working with numerous chip manufacturers to create

ultra-efficient, low-energy servers aimed at companies running large-scale remote computing operations such as Twitter and

Facebook

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POET can also produce an infra-red sensor for use in air, sea, ground, and space with sensitivity that is an order of magnitude higher than existing technology

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Sampling of Potential Market

Applications

Commercial

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CPU

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Memory

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Processor to Processor Optical Interconnect

Communications

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Smart Phones

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Network (Cell Towers, LANs, MANs)

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Fiber to the Home (FTTH)

Defense

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Infrared Sensors (Uncooled – SWIR, MWIR,

LWIR)

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Integrated photonics and electronics for:

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Radar and Lidar

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Communications

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Displays

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Hardened computers and memory

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Microwave and millimetre wave power

sources

Other

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Active Optical Cables

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Coherent laser arrays for pumps, industrial

applications

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Commercial UV/VIS/NIR cameras

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POET technology is applicable to a large portion of the total semiconductor market ($430 billion 2015 Forecast) as it is possibly the most comprehensive solution yet to increasing

semiconductor performance in an economic and functional manner

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In the near term, POET could potentially address the following markets:

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Optical semiconductor ($37.4 billion 2015 Forecast)

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Sensors and actuators ($14.1 billion 2015 Forecast)

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POET technology is applicable to a large portion of the total semiconductor market ($430 billion 2015 Forecast) as it is possibly the most comprehensive solution yet to increasing

semiconductor performance in an economic and functional manner

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In the near term, POET could potentially address the following markets:

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Optical semiconductor ($37.4 billion 2015 Forecast)

• Semiconductor Market

Forecasts (POET Markets)

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Analogue ICs ($55.9 billion 2015 Forecast)

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Discrete semiconductor ($28.6 billion 2015 Forecast)

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In the longer term, POET could potentially address the following markets:

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Logic ($114 billion 2015 Forecast)

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MPUs and MCUs ($92.6 billion 2015 Forecast)

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Memories ($86.6 billion 2015 Forecast)

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Quantum computing – Although quantum computing is in its infancy, POET can support quantum computing applications since it can support fabrication of quantum dot-based spin qubits and the devices needed to read and write them on the same die

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Analogue ICs ($55.9 billion 2015 Forecast)

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Discrete semiconductor ($28.6 billion 2015 Forecast)

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In the longer term, POET could potentially address the following markets:

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Logic ($114 billion 2015 Forecast)

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MPUs and MCUs ($92.6 billion 2015 Forecast)

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Memories ($86.6 billion 2015 Forecast)

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Quantum computing – Although quantum computing is in its infancy, POET can support quantum computing applications since it can support fabrication of quantum dot-based spin qubits and the devices needed to read and write them on the same die

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CMOS Silicon

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Final CMOS Si geometry (10/11 nm) is under development now; first production 2015?

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POET/PET offer about 100x speed improvement over CMOS silicon

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POET/PET offer 10-100x power efficiency improvement over CMOS silicon

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OE Conversion

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As example, current 10 Gigabit Ethernet transceivers use about 10 individually packaged ICs on a substrate in a die-cast housing; POET can reduce this to 1 individually packaged IC

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Depending on application, POET can reduce overall OE transceiver cost by 60 to 90%

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Memory and Storage

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CMOS Silicon

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Final CMOS Si geometry (10/11 nm) is under development now; first production 2015?

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POET/PET offer about 100x speed improvement over CMOS silicon

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POET/PET offer 10-100x power efficiency improvement over CMOS silicon

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OE Conversion

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As example, current 10 Gigabit Ethernet transceivers use about 10 individually packaged ICs on a substrate in a die-cast housing; POET can reduce this to 1 individually packaged IC

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Depending on application, POET can reduce overall OE transceiver cost by 60 to 90%

• Four Examples of POET

Value

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Current memory types include dedicated SRAM, DRAM, and NVRAM devices

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POET/PET memory cell can concurrently support all three memory types

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Massive simplification at system level due to elimination of NVRAM backup/recovery

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Much lower bit error rates than silicon-based memories (several orders of magnitude)

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Sensors and Weapons

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POET provides low-cost optical thyristor arrays that can be used as dual-mode sensor/laser arrays (same panel can find targets and destroy them)

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Main reason US Government funded research for so long (19 years and counting…)

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Current memory types include dedicated SRAM, DRAM, and NVRAM devices

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POET/PET memory cell can concurrently support all three memory types

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Massive simplification at system level due to elimination of NVRAM backup/recovery

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Much lower bit error rates than silicon-based memories (several orders of magnitude)

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Sensors and Weapons

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2.5 D Packaging

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Refers to die-stacking where multiple chips are put in a single package; often used for memory devices

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3 D Packaging

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Refers to true multiple-chip packaging where devices can be assembled in any orientation to one another in the vertical or horizontal plane

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Silicon Photonics

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Typically involves a passive silicon substrate providing optical (and often

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2.5 D Packaging

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Refers to die-stacking where multiple chips are put in a single package; often used for memory devices

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3 D Packaging

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Refers to true multiple-chip packaging where devices can be assembled in any orientation to one another in the vertical or horizontal plane

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Silicon Photonics

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Typically involves a passive silicon substrate providing optical (and often

Complementary

Technologies

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Typically involves a passive silicon substrate providing optical (and often electrical) interconnect between separate active devices attached to it

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Coherent Optics

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Module-level tunable integrated optical circuits for DWDM optical networking applications

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Typically involves a passive silicon substrate providing optical (and often electrical) interconnect between separate active devices attached to it

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Coherent Optics

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Module-level tunable integrated optical circuits for DWDM optical networking applications

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Monolithic Opto-Electronic Integration

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Very long development timelines (VC-backed startups have all failed)

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Dozens of companies have attempted at least some work in this area; considered to be the long-term industry “Holy Grail”

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Other efforts have favored optics over electronics (usually based on InP instead of GaAs)

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Competitive Activities

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Monolithic Opto-Electronic Integration

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Very long development timelines (VC-backed startups have all failed)

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Dozens of companies have attempted at least some work in this area; considered to be the long-term industry “Holy Grail”

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Other efforts have favored optics over electronics (usually based on InP instead of GaAs)

• Competitive Strength

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Intel has been working on monolithic integration for several years now; their internal efforts are estimated to be several years (at minimum) behind POET/PET

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Most industry efforts over last few years have been related to hybrid integration techniques like silicon photonics…

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InP-based processes developed to enable more optical integration, but pretty much useless for electrical applications

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Intel has been working on monolithic integration for several years now; their internal efforts are estimated to be several years (at minimum) behind POET/PET

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Most industry efforts over last few years have been related to hybrid integration techniques like silicon photonics…

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InP-based processes developed to enable more optical integration, but pretty much useless for electrical applications

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Several Options to Monetize POET

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POET is a research company, not a product company

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POET/PET are ready to enter the commercialization process

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No single company is currently active in all market areas where POET provides a best-in-class value proposition; syndicate needed to extract full value from technology

platform

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Single Acquirer

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This path would involve selling POET to a single (by definition large) 3rd _party

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Several Options to Monetize POET

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POET is a research company, not a product company

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POET/PET are ready to enter the commercialization process

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No single company is currently active in all market areas where POET provides a best-in-class value proposition; syndicate needed to extract full value from technology

platform

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Single Acquirer

• Monetization Paths

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Technology access/investment would likely be syndicated by acquirer

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Relatively small number of viable candidates

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Multiple Acquirers

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This path would involve selling POET to a syndicate (likely structured as a joint venture)

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Ideal syndicate would include members with market presence in all key areas related to POET commercialization

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Licensing

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Certain specialized market segments might be best addressed by licensing all or part of the POET/PET technology to one or more 3rd _{parties for use in a given market}

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Can be complex with difficult-to-foresee implications for other activities

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Technology access/investment would likely be syndicated by acquirer

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Relatively small number of viable candidates

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Multiple Acquirers

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This path would involve selling POET to a syndicate (likely structured as a joint venture)

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Ideal syndicate would include members with market presence in all key areas related to POET commercialization

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Licensing

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Certain specialized market segments might be best addressed by licensing all or part of the POET/PET technology to one or more 3rd _{parties for use in a given market}

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Technology Milestones

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Internal test chip development milestone list

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External (Independent Fabrication Facility) process validation milestone list

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Business Milestones

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Restructuring milestone list

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POET/PET monetization milestone list

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Technology Milestones

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Internal test chip development milestone list

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External (Independent Fabrication Facility) process validation milestone list

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Business Milestones

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Restructuring milestone list

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POET/PET monetization milestone list

Timeline Of Planned

Activities

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Milestone Terms and

Definitions

Milestone

# Previous Terminology Updated Terminology Definitions

1 Integrated Pulsed Laser Integrated Pulsed Laser General purpose laser for on-chip use.

2 Electrical Component Validation p and n channel Complementary Heterostructure Field Effect Transistor Validation

High performance, power efficient transistors. World’s first complementary GaAs HFETs.

3 Vertical Emitting Laser Continuous Wave Vertical Cavity Surface Emitting Laser Demonstration

High density laser design for surface-emitting applications (e.g. chip-to-chip in stacked-die array).

4 RF operation of n-channel and

p-n-channel and p-channel Complementary

Heterostructure Field Effect Transistor Radio Frequency Demonstrating radio frequency and microwave performance of

4 RF operation of n-channel and p-_{channel devices} Heterostructure Field Effect Transistor Radio Frequency Validation

Demonstrating radio frequency and microwave performance of revolutionary complementary HFETs.

5 Four-Terminal Switching Laser 3/4 Terminal Switching Laser Demonstration High quality pulsed laser type for critical signal propagation (e.g.

clocks, optical line signaling).

6 Complementary Inverter-_oscillator Complementary Heterostructure Field Effect_{Transistor-based Inverter/Oscillator Demonstration} Complementary HFET-based ring oscillator (standard circuit

configuration used to demonstrate process performance).

7 Optical Component Validation

Optical Thyristor-based Infrared Detector Array

Fabrication and Validation An array of optical thyristors configured as infrared detectors.

8 Feature Size Reduction Demonstration of 100 nm or below PET n- and p-channel device and ring oscillator

Demonstration of p and n type HFETs and BJTs at sub-100 nm feature size (smallest GaAs transistors in the world to date).

9 Integrated Optical Modulator _{Demonstration} Integrated External Modulator for Continuous Wave _{Laser Demonstration} High performance optical modulator for use with continuous wave

lasers (best performance for critical applications).

10 Monolithic Integration Full Integration of Electrical and Optical Devices on Single Die

Integration of all previously developed POET electrical and optical devices on a single die.

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Milestone Terms and

Definitions

Milestone

# Previous Terminology Updated Terminology Definitions

11 TDK (Technical Design Kit) Design rules and parameters library for POET platform.

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Targeted Development

Milestones

Q 2- 2011

p and n c hannel Com plem entar y Heter os tr uc tur e

F ield Ef f ec t T r ans is tor Validat ion

( 3r d _{Par ty F ab)}

See previous slide for definition of terms

Q 1- 2013

p and n c hannel Com plem entar y Heter os tr uc tur e

F ield Ef f ec t T r ans is tor Radio

F r equenc y Validation ( 3r d _{Par ty}

F ab)

Q 2- 2013

Com plem entar y Heter os tr uc tur e F ield Ef f ec t 1 um Tr a n s i s t o r - b a s e d I n v e r t e r / O s c i l l a t o r D e m o n s t r a t i o n ( P O E T L a b ) C o m p l e t e d a t r e q u e s t S S C p r i o r t o M i l e s t o n e 5 Q 1- 2014

Dem ons tr ation of

100nm or below PET n- and p-c hannel devip-c e ( PO ET Lab) Q 1- 2014 Full POET TDK D o c u m e n t a t i o n R e l e a s e ( u n d e r N D A ) Jan - 2014 3/4 T er m inal Switc hing Las er

Dem ons tr ation ( PO ET Lab)

Jan - 2014

O ptic al T hyr is to r -bas ed Inf r ar ed Detec tor Ar r a y F abr ic ation and Validation ( 3r d _{Par ty}

F ab)

Q 4- 2012

Continuous W ave Ver tic al Cavit y Sur f ac e Em itting Las er Dem ons tr ation

( PO ET Lab) = Milestone Accomplished

1

2

3

4

6

Q 2- 2011 Integr ated Puls ed Las er Dem ons tr ation

( PO ET Lab)

= CHANGES BY SSC

8

11

SSC Decision - Milestone #9 and #10 TBA

P O E T t e a m i s i m p a c t e d b y MB E m a i n t e n a n c e a n d n e e d s t o f o c u s o n TD K p r e p a r a t i o n . O n c e o u r m a i n c o m m e r c i a l p a r t n e r i s n a m e d , t h e P O E T p r i o r i t i e s wi l l b e d r i v e n b y t h e P D A ( P O E T D e v e l o p m e n t A l l i a n c e ) F eb - 2014 4 week s f or MBE planned m aintenanc e

12

Q 3- 2014 PET Electrical TDK E l e c t r i c a l Te c h n o l o g y D e s i g n K i t Mo d e l s a v a i l a b l e ( u n d e r N D A )

5

7

(24)

M arket s

• H igh Speed D igit al • M obile handheld • Base for m ost m arket s

• < 90 nm geomet ries • M ixed Signal/ A nalog

• A ut om ot ive

Enabling Markets and Partners

M ar ket s

• H igh Speed D igit al com plet e offering • FLA SH M em or y

• D RA M

• H igh Speed Opt ical • A ct ive op. cables

• D W D M

POET

POET D evelopm ent Team

Part ner Team (s)

Pha

se 1 _Phase 3

M ar ket s

• OE T ransceiver

• D at a cent er fiber int er connect • T OSA / ROSA

• H igh Speed Sync Logic

M arket s

• M M W t ransceivers • Radio over Fiber

POET Research Team

2014 – Recognition Year for POET

Phas

e 2 Phase

(25)

Paradigm-Changing

(26)

•

The silicon industry (and a myriad of system businesses it supports) has been looking for a new technology path for several years, with limited success and ever-increasing urgency…

•

POET/PET offer about 100x speed improvement over CMOS silicon (silicon hits a “power

wall” at about 4 GHz that has limited circuit speeds to about 3.2 GHz over the last 10 years)

•

POET/PET offer 10-100x power efficiency improvement over CMOS silicon (depending on

application)

•

The silicon industry (and a myriad of system businesses it supports) has been looking for a new technology path for several years, with limited success and ever-increasing urgency…

•

POET/PET offer about 100x speed improvement over CMOS silicon (silicon hits a “power

wall” at about 4 GHz that has limited circuit speeds to about 3.2 GHz over the last 10 years)

•

POET/PET offer 10-100x power efficiency improvement over CMOS silicon (depending on

application)

POET Potential Value For

the CMOS Silicon Industry

application)

•

Since POET/PET are CMOS technologies fabricated using standard lithography techniques, they are highly amenable to current semiconductor production facilities: no

retrofit/modifications to existing silicon fab’s to manufacture POET/PET-based wafers/devices

application)

•

Since POET/PET are CMOS technologies fabricated using standard lithography techniques, they are highly amenable to current semiconductor production facilities: no

retrofit/modifications to existing silicon fab’s to manufacture POET/PET-based wafers/devices

(27)

•

Total sales in the semiconductor industry will be over $430B in 2014

•

CMOS silicon is the dominant technology in use today by the semiconductor industry, accounting for over 90% of the total wafer area fabricated in 2012

•

CMOS silicon has supported a doubling of circuit density every 18 months or so since the early 1960s; this phenomenon is referred to as “Moore’s Law” after the man who first predicted this would occur and continue for decades (Dr. Gordon Moore, co-founder of Intel Corp)

•

Total sales in the semiconductor industry will be over $430B in 2014

•

CMOS silicon is the dominant technology in use today by the semiconductor industry, accounting for over 90% of the total wafer area fabricated in 2012

•

CMOS silicon has supported a doubling of circuit density every 18 months or so since the early 1960s; this phenomenon is referred to as “Moore’s Law” after the man who first predicted this would occur and continue for decades (Dr. Gordon Moore, co-founder of Intel Corp)

POET Potential Value For

the CMOS Silicon Industry

would occur and continue for decades (Dr. Gordon Moore, co-founder of Intel Corp)

•

This continuous improvement in technology capability has been the key growth enabler in the overall tech business for the last 50 years, and it’s just about over…

•

Final CMOS silicon geometry (10/11 nm) is under development now, with first production planned for 2015; quantum effects preclude further transistor size reductions, and any

meaningful performance improvements stopped several years ago (e.g. CPU execution unit speeds haven’t improved in over 10 years)

would occur and continue for decades (Dr. Gordon Moore, co-founder of Intel Corp)

•

This continuous improvement in technology capability has been the key growth enabler in the overall tech business for the last 50 years, and it’s just about over…

•

Final CMOS silicon geometry (10/11 nm) is under development now, with first production planned for 2015; quantum effects preclude further transistor size reductions, and any

meaningful performance improvements stopped several years ago (e.g. CPU execution unit speeds haven’t improved in over 10 years)

(28)

Integrated Mobile

Typical Mobile Device

Architecture Today

Integrated Mobile Processor Baseband Radio Frequency Memory NVRAM

(29)

POET-Enabled Mobile

Device Architecture

Full Monolithic Integrated Mobile Device

(30)

•

OE conversion modules are used whenever an electrical/electronic system (e.g. a compute server, storage array, switch, router, etc) is connected to an optical fiber network

•

Today these modules consist of several discrete integrated circuits (ICs, or “chips”) of different materials and processes

•

POET offers the capability to integrate the entire OE conversion function from electrical connector to fiber connector in a single IC:

•

OE conversion modules are used whenever an electrical/electronic system (e.g. a compute server, storage array, switch, router, etc) is connected to an optical fiber network

•

Today these modules consist of several discrete integrated circuits (ICs, or “chips”) of different materials and processes

•

POET offers the capability to integrate the entire OE conversion function from electrical connector to fiber connector in a single IC:

POET Potential Value For

the OE Conversion Industry

connector to fiber connector in a single IC:

•

for example, current 10 Gigabit Ethernet transceivers use about 10 individually packaged ICs on a substrate in a die-cast housing;

•

POET can reduce this to 1 individually packaged IC

•

An OE module based on the POET technology offers tremendous cost savings; depending on

application overall module cost can be reduced by 60 to 90% through a combination of assembly, test, bill of materials, and reliability improvements

•

POET can support integration of the entire OE interface into a larger digital device like a CPU, NPU, integrated switch, etc; this will enable (for the first time) single-chip systems with direct optical-fiber attachment

connector to fiber connector in a single IC:

•

for example, current 10 Gigabit Ethernet transceivers use about 10 individually packaged ICs on a substrate in a die-cast housing;

•

POET can reduce this to 1 individually packaged IC

•

An OE module based on the POET technology offers tremendous cost savings; depending on

application overall module cost can be reduced by 60 to 90% through a combination of assembly, test, bill of materials, and reliability improvements

•

POET can support integration of the entire OE interface into a larger digital device like a CPU, NPU, integrated switch, etc; this will enable (for the first time) single-chip systems with direct optical-fiber attachment

(31)

Laser Diode Laser

Driver

10 Gigabit Optical

Transceiver Today: 9 Chips

SerDes/C DR Limiting Amplifier Detector Trans Impedanc e Amplifier Micro Controller Memory NVRAM

(32)

POET-Enabled 10 Gigabit

Optical Transceiver: 1 Chip!!

(33)

•

Current semiconductor random-access memory (RAM) types include dedicated Static RAM (SRAM), Dynamic RAM (DRAM), and Non-Volatile RAM (NVRAM); each type has certain advantages/disadvantages depending on application

•

Modern electronic systems invariably require a mix of all three types

•

SRAM cell arrays are (typically) embedded in larger chips like CPUs, NPUs, etc. for high performance applications like on-chip cache in CPUs

•

Current semiconductor random-access memory (RAM) types include dedicated Static RAM

(SRAM), Dynamic RAM (DRAM), and Non-Volatile RAM (NVRAM); each type has certain advantages/disadvantages depending on application

•

Modern electronic systems invariably require a mix of all three types

•

SRAM cell arrays are (typically) embedded in larger chips like CPUs, NPUs, etc. for high performance applications like on-chip cache in CPUs

POET Potential Value For

the Memory Industry

performance applications like on-chip cache in CPUs

•

DRAM cell arrays are almost entirely implemented in stand-alone memory chips (and put on DIMMs…) and are much more dense and power efficient than SRAM

•

NVRAM cell arrays are entirely implemented in stand-alone memory chips (e.g. flash memory devices used for solid state hard drives in mobile devices)

•

POET/PET support the fabrication of memory cells that can concurrently support all three types of memory operation

•

Offers massive simplification at system level due to elimination of NVRAM backup/recovery performance applications like on-chip cache in CPUs

•

DRAM cell arrays are almost entirely implemented in stand-alone memory chips (and put on DIMMs…) and are much more dense and power efficient than SRAM

•

NVRAM cell arrays are entirely implemented in stand-alone memory chips (e.g. flash memory devices used for solid state hard drives in mobile devices)

•

POET/PET support the fabrication of memory cells that can concurrently support all three types of memory operation

(34)

•

Much lower bit error rates than silicon-based memories (several orders of magnitude) due to inherent physical properties of Gallium Arsenide versus Silicon

•

Can achieve densities comparable to modern DRAM and speeds up to 100x faster than current SRAM

•

Due to the tri-mode capability, system memory requirements are significantly reduced; depending on application, system memory capital cost would be reduced by 20 to 50%

•

Much lower bit error rates than silicon-based memories (several orders of magnitude) due to inherent physical properties of Gallium Arsenide versus Silicon

•

Can achieve densities comparable to modern DRAM and speeds up to 100x faster than current SRAM

•

Due to the tri-mode capability, system memory requirements are significantly reduced; depending on application, system memory capital cost would be reduced by 20 to 50%

POET Potential Value For

the Memory Industry

depending on application, system memory capital cost would be reduced by 20 to 50%

•

For the same reason as above, again depending on application system memory power

consumption would be reduced by 25 to 80%

•

Today storage RAID systems require battery backup to save striping and encoding configurations in case of system power loss; each server RAID card needs a battery

comparable in size to those used in laptops for this purpose, plus sufficient dedicated flash memory to store the entire subsystem configuration; this represents a significant cost addition (~$100/unit) and a significant safety/fire hazard in data center environments

depending on application, system memory capital cost would be reduced by 20 to 50%

•

For the same reason as above, again depending on application system memory power

consumption would be reduced by 25 to 80%

•

Today storage RAID systems require battery backup to save striping and encoding configurations in case of system power loss; each server RAID card needs a battery

comparable in size to those used in laptops for this purpose, plus sufficient dedicated flash memory to store the entire subsystem configuration; this represents a significant cost addition (~$100/unit) and a significant safety/fire hazard in data center environments

(35)

One Monolithic

Opto-Electronic Chip

(36)

•

POET arrays can be constructed to be flexible, allowing them to easily be attached to the surface of complex shapes like aircraft and ships, forming an “active skin”

•

This configuration will allow aircraft and ships to service targets much more quickly than the separate sensor-gun-missile systems that represent current state of the art

•

POET arrays can be constructed to be flexible, allowing them to easily be attached to the surface of complex shapes like aircraft and ships, forming an “active skin”

•

This configuration will allow aircraft and ships to service targets much more quickly than the separate sensor-gun-missile systems that represent current state of the art

POET Potential Value For Imaging

Sensors and Directed Energy Arrays

separate sensor-gun-missile systems that represent current state of the art

•

Due to the inherent physical properties of GaAs, POET sensor arrays can achieve superior resolution for SWIR, MWIR, and LWIR applications to the best silicon sensors currently

available, and can achieve this performance without the elaborate and heavy electromagnetic shielding and liquid nitrogen cryogenic cooling required by silicon-based systems

•

Main reason the US Government has funded research for so long (19 years and counting…) separate sensor-gun-missile systems that represent current state of the art

•

Due to the inherent physical properties of GaAs, POET sensor arrays can achieve superior resolution for SWIR, MWIR, and LWIR applications to the best silicon sensors currently

available, and can achieve this performance without the elaborate and heavy electromagnetic shielding and liquid nitrogen cryogenic cooling required by silicon-based systems

(37)

••

For commercial applications POET offers tremendous cost savings for implementing laser-array-based systems like 3D holographic displays (could put one on a cell phone for about $15),

directed energy tools (e.g. micro-assemblers), machine vision, low-cost night vision and active imaging and ranging for automotive applications, etc. etc. etc.

POET Potential Value For Imaging

Sensors and Directed Energy Arrays

(38)

•

Finally Ready to Show the World

•

Very long technology development timeline (23 years and counting…)

•

Recently started building test chips to show POET capabilities to interested 3rd _parties