V DSS R DS(on) max I D. 20V GS = 10V 8.9A. 71 P A = 25 C Power Dissipation 2.0 P A = 70 C Power Dissipation Linear Derating Factor

www.irf.com 1

IRF8915PbF

HEXFET

Power MOSFET

Notes  through

are on page 10 Benefits

l

Ultra-Low Gate Impedance

l

Very Low R

l

Fully Characterized Avalanche Voltage and Current

SO-8 Applications

Dual SO-8 MOSFET for POL converters in desktop, servers, graphics cards, game consoles and set-top box

l

Lead-Free

D1 D1 D2 D2 G1

S2 G2 S1

Top View

1 8 2 3

4 5

6 7

V _DSS R _DS(on) max I _D

20V 18.3m:@V

= 10V 8.9A

Absolute Maximum Ratings

Parameter Units

VDS Drain-to-Source Voltage V

V_GS Gate-to-Source Voltage

I_D @ TA = 25°C Continuous Drain Current, VGS @ 10V

I_D @ TA = 70°C Continuous Drain Current, VGS @ 10V A

I_DM Pulsed Drain Current c

PD @TA = 25°C Power Dissipation W

P_D @TA = 70°C Power Dissipation

Linear Derating Factor W/°C

T_J Operating Junction and °C

TSTG Storage Temperature Range

Thermal Resistance

Parameter Typ. Max. Units

R_θJL Junction-to-Drain Lead ––– 42 °C/W

RθJA Junction-to-Ambient f ––– 62.5

-55 to + 150 2.0

0.016 1.3 Max.

8.9 7.1 71 ± 20

20

PD -95727A

IRF8915PbF

S D

G

Static @ T

= 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units

BVDSS Drain-to-Source Breakdown Voltage 20 ––– ––– V

∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.015 ––– V/°C

RDS(on) Static Drain-to-Source On-Resistance ––– 14.6 18.3 mΩ

––– 21.6 27

VGS(th) Gate Threshold Voltage 1.7 ––– 2.5 V

∆VGS(th)/∆TJ Gate Threshold Voltage Coefficient ––– -4.8 ––– mV/°C

IDSS Drain-to-Source Leakage Current ––– ––– 1.0 µA

––– ––– 150

IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA

Gate-to-Source Reverse Leakage ––– ––– -100

gfs Forward Transconductance 12 ––– ––– S

Qg Total Gate Charge ––– 4.9 7.4

Qgs1 Pre-Vth Gate-to-Source Charge ––– 1.8 –––

Qgs2 Post-Vth Gate-to-Source Charge ––– 0.61 ––– nC

Qgd Gate-to-Drain Charge ––– 1.7 –––

Qgodr Gate Charge Overdrive ––– 0.79 ––– See Fig. 6

Qsw Switch Charge (Qgs2 + Qgd) ––– 2.3 –––

Qoss Output Charge ––– 2.7 ––– nC

td(on) Turn-On Delay Time ––– 6.0 –––

tr Rise Time ––– 12 ––– ns

td(off) Turn-Off Delay Time ––– 7.1 –––

tf Fall Time ––– 3.6 –––

Ciss Input Capacitance ––– 540 –––

Coss Output Capacitance ––– 180 ––– pF

Crss Reverse Transfer Capacitance ––– 91 –––

Avalanche Characteristics

Parameter Units

EAS Single Pulse Avalanche Energy d mJ

IAR Avalanche Current c A

Diode Characteristics

Parameter Min. Typ. Max. Units

IS Continuous Source Current ––– ––– 2.5

(Body Diode) A

ISM Pulsed Source Current ––– ––– 71

(Body Diode)c

VSD Diode Forward Voltage ––– ––– 1.0 V

trr Reverse Recovery Time ––– 13 19 ns

Qrr Reverse Recovery Charge ––– 3.5 5.2 nC

–––

ID = 7.1A

VGS = 0V VDS = 10V

VGS = 4.5V, ID = 7.1A e

VGS = 4.5V

Typ.

–––

VDS = VGS, ID = 250µA

Clamped Inductive Load VDS = 10V, ID = 7.1A

VDS = 16V, VGS = 0V, TJ = 125°C

T_J = 25°C, I_F = 7.1A, VDD = 10V di/dt = 100A/µs e

TJ = 25°C, IS = 7.1A, VGS = 0V e showing the

integral reverse p-n junction diode.

MOSFET symbol VDS = 10V, VGS = 0V VDD = 4.5V, VGS = 4.5V ID = 7.1A

VDS = 10V VGS = 20V VGS = -20V

VDS = 16V, VGS = 0V Conditions VGS = 0V, ID = 250µA Reference to 25°C, ID = 1mA VGS = 10V, ID = 8.9A e

Conditions Max.

15 7.1 ƒ = 1.0MHz

IRF8915PbF

Fig 4. Normalized On-Resistance vs. Temperature

Fig 2. Typical Output Characteristics Fig 1. Typical Output Characteristics

Fig 3. Typical Transfer Characteristics

0.1 1 10 100

VDS, Drain-to-Source Voltage (V) 0.001

0.01 0.1 1 10 100

I D, Drain-to-Source Current (A)

VGS TOP 10V

8.0V 5.5V 4.5V 3.5V 3.0V 2.8V

BOTTOM 2.5V

≤60µs PULSE WIDTH Tj = 25°C

2.5V

0.1 1 10 100

VDS, Drain-to-Source Voltage (V) 0.1

1 10 100

I D, Drain-to-Source Current (A)

2.5V

≤60µs PULSE WIDTH Tj = 150°C

VGS TOP 10V

8.0V 5.5V 4.5V 3.5V 3.0V 2.8V

BOTTOM 2.5V

1 2 3 4 5 6 7

VGS, Gate-to-Source Voltage (V) 0.1

1 10 100

ΑI D, Drain-to-Source Current ()

TJ = 25°C TJ = 150°C

VDS = 10V

≤60µs PULSE WIDTH

-60 -40 -20 0 20 40 60 80 100 120 140 160 TJ , Junction Temperature (°C)

0.5 1.0 1.5

RDS(on) , Drain-to-Source On Resistance (Normalized)

ID = 8.9A VGS = 10V

IRF8915PbF

Fig 8. Maximum Safe Operating Area Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage Fig 5. Typical Capacitance vs.

Drain-to-Source Voltage

Fig 7. Typical Source-Drain Diode Forward Voltage

1 10 100

VDS, Drain-to-Source Voltage (V) 10

100 1000 10000

C, Capacitance(pF)

VGS = 0V, f = 1 MHZ

Ciss = Cgs + Cgd, C ds SHORTED Crss = Cgd

Coss = Cds + Cgd

Coss Crss Ciss

0 1 2 3 4 5 6 7

QG Total Gate Charge (nC) 0.0

1.0 2.0 3.0 4.0 5.0 6.0

VGS, Gate-to-Source Voltage (V) VDS= 16V VDS= 10V ID= 7.1A

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VSD, Source-to-Drain Voltage (V) 0.10

1.00 10.00 100.00

I S, Reverse Drain Current (A)D

TJ = 25°C TJ = 150°C

VGS = 0V

0 1 10 100 1000

VDS, Drain-to-Source Voltage (V) 0.1

1 10 100 1000

I D, Drain-to-Source Current (A)

1msec 10msec OPERATION IN THIS AREA LIMITED BY R DS(on)

100µsec

TA = 25°C Tj = 150°C Single Pulse

IRF8915PbF

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient Fig 9. Maximum Drain Current vs.

Ambient Temperature Fig 10. Threshold Voltage vs. Temperature

25 50 75 100 125 150

TA , Ambient Temperature (°C) 0

1 2 3 4 5 6 7 8 9

I D,

Drain Current (A)

-75 -50 -25 0 25 50 75 100 125 150 TJ , Temperature ( °C )

1.0 1.5 2.0 2.5 3.0

VGS(th) Gate threshold Voltage (V)

ID = 250µA

1E-006 1E-005 0.0001 0.001 0.01 0.1 1 10 100

t1 , Rectangular Pulse Duration (sec) 0.01

0.1 1 10 100

Thermal Response ( Z thJA ) 0.20

0.10 D = 0.50

0.02 0.01 0.05

SINGLE PULSE

( THERMAL RESPONSE )

Notes:

1. Duty factor D = t / t 2. Peak T J= PDMx Z¹ thJA² + TA

P t

t DM

1 2

τ_J τ_J

τ₁ τ₁

τ₂ τ₂

τ₃ τ₃ R₁

R₁ R₂ R₂

R₃ R₃

Ci i/Ri Ci= τi/Ri

τ_Cτ τ₄ τ₄

R₄

R₄ Ri (°C/W) τi (sec) 3.68799 0.000349 2.18971 0.005246 34.7298 0.470610 21.8971 13.52000

IRF8915PbF

Fig 13. Maximum Avalanche Energy vs. Drain Current

Fig 16. Switching Time Test Circuit Fig 17. Switching Time Waveforms Fig 12. On-Resistance vs. Gate Voltage

D.U.T. V_DS

I_D I_G 3mA V_GS

.3µF 50KΩ 12V .2µF

Current Regulator Same Type as D.U.T.

Current Sampling Resistors + -

Fig 15. Gate Charge Test Circuit Fig 14. Unclamped Inductive Test Circuit

and Waveform

tp

V(BR)DSS

IAS RG

IAS 0.01Ω tp

D.U.T VDS L

+ - VDD DRIVER

A 15V

20VVGS

V_GS

Pulse Width < 1µs Duty Factor < 0.1%

V_DD V_DS

L_D

D.U.T +

-

V

V

10%

t_d(on) t_r t_d(off) t_f

1 2 3 4 5 6 7 8 9 10

VGS, Gate -to -Source Voltage (V) 10

15 20 25 30 35 40

RDS(on), Drain-to -Source On Resistance (mΩ)

ID = 8.9A

TJ = 125°C TJ = 25°C

25 50 75 100 125 150

Starting TJ , Junction Temperature (°C) 0

10 20 30 40 50 60

EAS , Single Pulse Avalanche Energy (mJ) ID

TOP 2.4A 2.9A BOTTOM 7.1A

IRF8915PbF

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET

Power MOSFETs

Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer

P.W. Period

di/dt Diode Recovery

dv/dt

Ripple ≤ 5%

Body Diode Forward Drop Re-Applied

Voltage Reverse Recovery

Current Body Diode Forward

Current

V_GS=10V

V_DD

I_SD Driver Gate Drive

D.U.T. I_SDWaveform

D.U.T. V_DSWaveform

Inductor Curent

D = P.W.

Period

*

*

+ - +

+

+ - -

-

ƒ

‚ „

RG • dv/dt controlled by RG VDD

• Driver same type as D.U.T.

• I_SD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

D.U.T



Fig 16. Gate Charge Waveform

Vgs Id

Vgs(th)

Qgs1 Qgs2 Qgd Qgodr

IRF8915PbF

Control FET

Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2.

Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses.

Power losses in the control switch Q1 are given by;

P

= P

+ P

+ P

+ P

This can be expanded and approximated by;

P

= I (

× R

)

+ I × Q

i

× V

× f

⎛

⎝ ⎜ ⎞

⎠ ⎟ + I × Q

i

× V

× f

⎛

⎝ ⎜ ⎞

⎠ ⎟ + Q (

× V

× f )

+ Q

2 ×V

× f

⎛ ⎝ ⎞

⎠

This simplified loss equation includes the terms Qgs2

and Q_oss which are new to Power MOSFET data sheets.

Q_gs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets.

The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16.

Q_gs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain cur- rent rises to Idmax at which time the drain voltage be- gins to change. Minimizing Q_gs2 is a critical factor in reducing switching losses in Q1.

Q_oss is the charge that must be supplied to the out- put capacitance of the MOSFET during every switch- ing cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (non- linear) capacitance’s C_ds and C_dg when multiplied by the power supply input buss voltage.

Synchronous FET

The power loss equation for Q2 is approximated by;

P

= P

+ P

+ P

P

= I (

× R

)

+ Q (

× V

× f )

+ Q

2 × V

× f

⎛

⎝ ⎜ ⎞

⎠ + Q (

× V

× f )

*dissipated primarily in Q1.

For the synchronous MOSFET Q2, R_ds(on) is an im- portant characteristic; however, once again the im- portance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the con- trol IC so the gate drive losses become much more significant. Secondly, the output charge Q_oss and re- verse recovery charge Q_rr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on.

The drain of Q2 is connected to the switching node of the converter and therefore sees transitions be- tween ground and V_in. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is ca- pacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Q_gd/Q_gs1 must be minimized to reduce the potential for Cdv/dt turn on.

Power MOSFET Selection for Non-Isolated DC/DC Converters

Figure A: Q_oss Characteristic

IRF8915PbF

SO-8 Package Outline (Mosfet & Fetky)

H  ' (

\ E

$

$

+ . /





ƒ



%$6,&















ƒ





























ƒ

%$6,&

















0,1 0$;

0,//,0(7(56 ,1&+(6

0,1 0$;

',0

ƒ

H

F    

%$6,& %$6,&

 



 

' %

(

$

; H

+

>@ $



 .[ƒ

;/ ;F

\

>@ & $ %

H $

;E $

&

>@





 

)22735,17

;>@

>@

;>@ ;>@

287/,1(&21)250672-('(&287/,1(06$$

127(6

',0(16,21,1* 72/(5$1&,1*3(5$60(<0

&21752//,1*',0(16,210,//,0(7(5

',0(16,216$5(6+2:1,10,//,0(7(56>,1&+(6@

',0(16,21'2(6127,1&/8'(02/'3527586,216

',0(16,21'2(6127,1&/8'(02/'3527586,216

02/'3527586,21612772(;&(('>@

',0(16,21,67+(/(1*7+2)/($')2562/'(5,1*72

$68%675$7(

02/'3527586,21612772(;&(('>@

Dimensions are shown in milimeters (inches)

SO-8 Part Marking Information

3 ',6*1$7(6/($')5((

(;$03/(7+,6,6$1,5)026)(7

);;;;

,17(51$7,21$/

/2*2 5(&7,),(5

3$57180%(5 /27&2'(

352'8&7237,21$/

'$7(&2'(<::

< /$67',*,72)7+(<($5 :: :((.

$ $66(0%/<6,7(&2'(

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/

IRF8915PbF

Notes:

 Repetitive rating; pulse width limited by max. junction temperature.

‚ Starting TJ = 25°C, L = 0.59mH, RG = 25Ω, IAS = 7.1A.

ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.

„When mounted on 1 inch square copper board.

… ^R_θ is measured at T_J of approximately 90°C.

330.00 (12.992) MAX.

14.40 ( .566 ) 12.40 ( .488 ) NOTES :

1. CONTROLLING DIMENSION : MILLIMETER.

2. OUTLINE CONFORMS TO EIA-481 & EIA-541.

FEED DIRECTION TERMINAL NUMBER 1

12.3 ( .484 ) 11.7 ( .461 )

8.1 ( .318 ) 7.9 ( .312 )

NOTES:

1. CONTROLLING DIMENSION : MILLIMETER.

2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).

3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

SO-8 Tape and Reel

Dimensions are shown in millimeters (inches)

Data and specifications subject to change without notice.

This product has been designed and qualified for the Consumer market.

Qualifications Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.07/2008 Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

IMPORTANT NOTICE

The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”) . With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party.

In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications.

The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application.

For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office (www.infineon.com).

WARNINGS

Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office.

Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.