Power MOSFET. IRF510PbF SiHF510-E3 IRF510 SiHF510. PARAMETER SYMBOL LIMIT UNIT Drain-Source Voltage V DS 100 V Gate-Source Voltage V GS ± 20

S15-2693-Rev. C, 16-Nov-15 Document Number: 91015

Power MOSFET

FEATURES

• Dynamic dV/dt rating

• Repetitive avalanche rated

• 175 °C operating temperature

• Fast switching

• Ease of paralleling

• Simple drive requirements

• Material categorization: for definitions of compliance please see www.vishay.com/doc?99912

Note

*

RoHS-compliant and / or parts that are non-RoHS-compliant. For

example, parts with lead (Pb) terminations are not RoHS-compliant.

Please see the information / tables in this datasheet for details.

DESCRIPTION

Third generation power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. 

The TO-220AB package is universally preferred for all commercial-industrial applications at power dissipation levels to approximately 50 W. The low thermal resistance and low package cost of the TO-220AB contribute to its wide acceptance throughout the industry.

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).

b. VDD = 25 V, starting TJ = 25 °C, L = 4.8 mH, Rg = 25 , IAS = 5.6 A (see fig. 12).

c. ISD  5.6 A, dI/dt  75 A/μs, VDD  VDS, TJ  175 °C.

d. 1.6 mm from case.

PRODUCT SUMMARY

VDS (V) 100

R_DS(on) () V_GS = 10 V 0.54

Qg max. (nC) 8.3

Qgs (nC) 2.3

Qgd (nC) 3.8

Configuration Single

N-Channel MOSFET G

D

S TO-220AB

GDS

Available Available

ORDERING INFORMATION INFORMATION

Package TO-220AB

Lead (Pb)-free IRF510PbF

SiHF510-E3

SnPb IRF510

SiHF510

ABSOLUTE MAXIMUM RATINGS (T

= 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage VDS 100

Gate-Source Voltage V_GS ± 20 V

Continuous Drain Current V_GS at 10 V TC = 25 °C

I_D 5.6

A

TC = 100 °C 4.0

Pulsed Drain Current ^a I_DM 20

Linear Derating Factor 0.29 W/°C

Single Pulse Avalanche Energy ^b EAS 75 mJ

Repetitive Avalanche Current ^a IAR 5.6 A

Repetitive Avalanche Energy ^a E_AR 4.3 mJ

Maximum Power Dissipation T_C = 25 °C P_D 43 W

Peak Diode Recovery dV/dt ^c dV/dt 5.5 V/ns

Operating Junction and Storage Temperature Range TJ, Tstg -55 to +175 Soldering Recommendations (Peak temperature) ^d for 10 s 300 °C

Mounting Torque 6-32 or M3 screw 10 lbf · in

1.1 N · m

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).

b. Pulse width  300 μs; duty cycle  2 %.

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT

Maximum Junction-to-Ambient RthJA - 62

°C/W

Case-to-Sink, Flat, Greased Surface R_thCS 0.50 -

Maximum Junction-to-Case (Drain) RthJC - 3.5

SPECIFICATIONS (T

= 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 μA 100 - - V V_DS Temperature Coefficient VDS/T_J Reference to 25 °C, I_D = 1 mA - 0.12 - V/°C Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V

Gate-Source Leakage IGSS VGS = ± 20 V - - ± 100 nA

Zero Gate Voltage Drain Current IDSS

VDS = 100 V, VGS = 0 V - - 25

μA V_DS = 80 V, V_GS = 0 V, T_J = 150 °C - - 250 Drain-Source On-State Resistance RDS(on) VGS = 10 V ID =3.4 A ^b - - 0.54 

Forward Transconductance gfs VDS = 50 V, ID = 3.4 A ^b 1.3 - - S

Dynamic

Input Capacitance C_iss V_GS = 0 V,

VDS = 25 V, f = 1.0 MHz, see fig. 5

- 180 -

Output Capacitance Coss - 81 - pF

Reverse Transfer Capacitance C_rss - 15 -

Total Gate Charge Qg

VGS = 10 V

I_D = 5.6 A, V_DS = 80 V VDS = 10 V, see fig. 6 and fig. 13 ^b

- - 8.3

nC

Gate-Source Charge Qgs - - 2.3

Gate-Drain Charge Qgd - - 3.8

Turn-On Delay Time t_d(on)

VDD = 50 V, ID = 5.6 A Rg = 24 , RD = 8.4, see fig. 10 ^b

- 6.9 -

Rise Time tr - 16 - ns

Turn-Off Delay Time td(off) - 15 -

Fall Time t_f - 9.4 -

Internal Drain Inductance LD Between lead,

6 mm (0.25") from package and center of die contact

- 4.5 -

nH

Internal Source Inductance L_S - 7.5 -

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current IS MOSFET symbol

showing the  integral reverse

p - n junction diode

- - 5.6

A

Pulsed Diode Forward Current^a ISM - - 20

Body Diode Voltage VSD TJ = 25 °C, IS = 5.6 A, VGS = 0 V ^b - - 2.5 V Body Diode Reverse Recovery Time trr

T_J = 25 °C, I_F = 5.6 A, dI/dt = 100 A/μs ^b

- 100 200 ns

Body Diode Reverse Recovery Charge Qrr - 0.44 0.88 μC

Forward Turn-On Time t_on Intrinsic turn-on time is negligible (turn-on is dominated by L_S and L_D)

D

S G

S D

G

S15-2693-Rev. C, 16-Nov-15 Document Number: 91015

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Fig. 1 - Typical Output Characteristics, T_C = 25 °C

Fig. 2 - Typical Output Characteristics, T_C = 175 °C

Fig. 3 - Typical Transfer Characteristics

Fig. 4 - Normalized On-Resistance vs. Temperature

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

91015_01

20 µs pulse width T_C = 25 °C

4.5 V

V

, Drain-to-Source Voltage (V) I

, Dr ain Current (A)

10¹

Bottom Top

V_GS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V 4.5 V 10⁰

10^-1 10⁰ 10¹

10¹

10⁰

10^-1 10⁰ 10¹

V

Drain-to-Source Voltage (V)

I

, Dr ain Current (A)

Bottom Top

V_GS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V 4.5 V

20 µs pulse width T_C = 175 °C

91015_02

20 µs pulse width V_DS = 50 V 10¹

10⁰

10^-1

I

, Dr ain Current (A)

V

Gate-to-Source Voltage (V)

5 6 7 8 9 10

4

25

°

175

°

91015_03

I_D= 5.6 A V_GS= 10 V 3.0

0.0 0.5 1.0 1.5 2.0 2.5

- 60 - 40 - 20 0 20 40 60 80 100 120 140 160

T

Junction Temperature (°C) R

, Dr ain-to-Source On Resistance (Nor maliz ed)

91015_04

180

400

320

240

160

0 80

10⁰ 10¹

V_GS = 0 V, f = 1 MHz C_iss = C_gs + C_gd, C_ds shorted C_rss = C_gd

C_oss = C_ds + C_gd

C_iss

C_rss C_oss

Capacitance (pF)

V

Drain-to-Source Voltage (V)

91015_05

20

16

12

8

0 4

0 2 4 6 8

I_D = 5.6 A

V_DS = 20 V

For test circuit see figure 13

10 V_DS = 50 V

V_DS = 80 V

Q

, Total Gate Charge (nC) V

, Gate-to-Source V o ltage (V)

91015_06

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 8 - Maximum Safe Operating Area

Fig. 9 - Maximum Drain Current vs. Case Temperature

Fig. 10a - Switching Time Test Circuit

Fig. 10b - Switching Time Waveforms

91015_07

25

°

°

V_GS= 0 V 10^-1

10⁰

V

, Source-to-Drain Voltage (V) I

, Re v erse Dr ain Current (A)

0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2

100 µs

1 ms

10 ms Operation in this area limited

by R_DS(on)

V

, Drain-to-Source Voltage (V) I

, Dr ain Current (A)

T_C = 25 °C T_J = 175 °C single pulse 0.1

10²

2 5

1

2 5

10

2 5

2 5

1 10 ^{2 5} 10^{2 2 5} 10³

91015_08

I

, Dr ain Current (A)

T

, Case Temperature (°C)

2.0 3.0 4.0 5.0 6.0

25 50 75 100 125 150

91015_09

0.0

175

Pulse width ≤ 1 µs Duty factor ≤ 0.1 %

R_D

V_GS R_G

D.U.T.

10 V

+- V_DS

V_DD

V_DS 90 %

10 % V_GS

t_d(on) t_r t_d(off) t_f

10

1

0.1

10^-2

10^-5 10^-4 10^-3 10^-2 0.1 1 10

P_DM

t₁ t₂

t

, Rectangular Pulse Duration (s) Ther mal Response (Z

)

Notes:

1. Duty factor, D = t₁/t₂ 2. Peak T_j = P_DM x Z_thJC + T_C Single pulse

(thermal response) 0 - 0.5

0.2 0.1 0.05 0.02 0.01

91015_11

S15-2693-Rev. C, 16-Nov-15 Document Number: 91015 Fig. 12a - Unclamped Inductive Test Circuit

Fig. 12b - Unclamped Inductive Waveforms

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Fig. 13a - Basic Gate Charge Waveform

Fig. 13b - Gate Charge Test Circuit

A

R_G

I_AS 0.01 Ω tp

D.U.T L V_DS

+ -V_DD 10 V

Vary t_p to obtain required IAS

I_AS V_DS

V_DD V_DS t_p

300

0 50 100 150 200 250

25 50 75 100 125 150

Starting T_J, Junction Temperature (°C)

E

, Single Pulse Energy (mJ)

Bottom Top

I_D 2.3 A 4.0 A 5.6 A

V_DD = 25 V

91015_12c

175

Q_GS Q_GD Q_G

V

Charge

D.U.T.

3 mA

V_GS

V_DS

I_G I_D

0.3 µF 0.2 µF

50 kΩ 12 V

Current regulator

Current sampling resistors Same type as D.U.T.

+ -

Fig. 14 - For N-Channel













Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and

P.W. Period

dI/dt Diode recovery

dV/dt

Ripple ≤ 5 %

Body diode forward drop Re-applied

voltage Reverse recovery current

Body diode forward current

V_GS = 10 V^a

I_SD Driver gate drive

D.U.T. l_SD waveform

D.U.T. V_DS waveform

Inductor current

D = P.W.

Period

+ - +

+

- + -

-

Peak Diode Recovery dV/dt Test Circuit

V_DD

• dV/dt controlled by Rg

• Driver same type as D.U.T.

• I_SD controlled by duty factor “D”

• D.U.T. - device under test D.U.T. Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance current transformer

R_g

Note

a. V_GS = 5 V for logic level devices

V_DD

www.vishay.com Vishay Siliconix

Revison: 14-Dec-15 Document Number: 66542

TO-220-1

Note

• M* = 0.052 inches to 0.064 inches (dimension including protrusion), heatsink hole for HVM

M^* 2 3

1

L L(1)

D H(1) Q

Ø P

A F

J(1) b(1)

e(1) e E

b

C

DIM. MILLIMETERS INCHES

MIN. MAX. MIN. MAX.

A 4.24 4.65 0.167 0.183

b 0.69 1.02 0.027 0.040

b(1) 1.14 1.78 0.045 0.070

c 0.36 0.61 0.014 0.024

D 14.33 15.85 0.564 0.624

E 9.96 10.52 0.392 0.414

e 2.41 2.67 0.095 0.105

e(1) 4.88 5.28 0.192 0.208

F 1.14 1.40 0.045 0.055

H(1) 6.10 6.71 0.240 0.264

J(1) 2.41 2.92 0.095 0.115

L 13.36 14.40 0.526 0.567

L(1) 3.33 4.04 0.131 0.159

Ø P 3.53 3.94 0.139 0.155

Q 2.54 3.00 0.100 0.118

ECN: X15-0364-Rev. C, 14-Dec-15 DWG: 6031

Package Picture

ASE Xi’an

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

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