Power Electronics Advanced

Preface

Power electronic converters have been used in wide range of

applications

including

home

appliances,

computers

and

telecommunication systems, motor drives and renewable energy

systems.

The main aim of publishing this book is to serve as a textbook for

undergraduate and postgraduate students who study Power Electronics

or Advanced Industrial Electronics subject or as a reference book for

development engineers who practice power electronics design.

I would like to thank Dr. Alireza Nami, Dr. Arash Abbasalizadeh

Boora and Dr. Jafar Adabi Firouzjaee who contributed in preparing

the following chapters.

This book consists of three main chapters which addresses important

topics in Power Electronics such as:

1: Multilevel Converter Topologies

This chapter describes traditional multilevel converter topologies with

different switching transients and voltage control of capacitors. It also

covers multilevel converters with new DC link configurations to

generate more voltage levels. In the final section, hybrid multilevel

converters with new and traditional DC link configurations are

discussed.

Authors: Dr. Alireza Nami, Prof. Firuz Zare

2: Single Inductor Multi-output DC-DC Converters

This chapter is focused on single inductor multi-output DC-DC

converters with series and parallel load configurations and based on

three traditional DC-DC converters: Buck, Boost and Positive Buck

Boost converters. Different operating modes of each converter have

been analysed based on different switching states and using

state-space averaged equations.

Authors: Dr. Arash Abbasalizadeh Boora, Prof. Firuz Zare

3: Analysis of Common Mode and Shaft Voltages in AC Motor

Drive Systems

The third chapter is about common mode voltage and shaft voltage

issues in AC motor drive systems. In the first part of this chapter,

three-phase pulse width modulated voltage waveforms (leg, line and

common mode voltages) generated by a power converter are analysed.

In the second part of this chapter, some methods to extract capacitive

couplings between windings, stator and rotor are described. Finally, a

high frequency model of an AC motor is discussed to calculate shaft

voltage and conducted emission noise.

Contents

1 Multilevel Converter Topologies

1.1

Symmetrical Multilevel Converters 2

1.1.1

Introduction 2

1.1.2

Diode-clamped Converter Topology 7

1.1.2.1

Single-phase Diode-clamped Converter 13

1.1.2.2

Three-phase Three-level Diode-clamped Converter 19

1.1.2.3

Capacitor Voltage Control in Diode-clamped

Converters 23

1.1.3

Flying Capacitor Converter Topology 29

1.1.3.1

Single-phase Flying Capacitor Converter 34

1.1.3.2

Three-phase Three-level Flying Capacitor Converter

39

1.1.3.3

Capacitor Voltage Control in Flying Capacitor

Converter 41

1.1.4

Cascade Converter Topology 45

1.1.4.1

Three-Phase Five-level Cascade Converter 50

1.1.5

High-level Multilevel Topologies 51

1.1.5.1

Diode Clamped Converter 52

1.1.5.2

Flying Capacitor Converter 58

1.1.5.3

Cascade Converter Structure 61

1.1.6

Conclusions 64

1.2

Asymmetrical Multilevel Converters 65

1.2.1

Introduction 65

1.2.2

Unequal DC Link Configuration for Multilevel

Converters 67

1.2.3

Unequal DC Link Design Considerations 73

1.2.3.1

Adjacent Switching States 73

1.2.3.2

Capacitor Voltage Balancing 74

1.2.3.3

Voltage Rating of Switching Components 74

1.2.4

Asymmetrical Diode-clamped Converters 74

1.2.4.1

Adjacent Switching States 75

1.2.4.2

Capacitor Voltage Balancing 82

1.2.4.3

Voltage Rating of Switching Components 87

1.2.5

Asymmetrical Flying Capacitor Converter 89

1.2.5.1

Adjacent Switching States 90

1.2.5.2

Capacitor Voltage Balancing 93

1.2.6

Asymmetrical Cascaded H-bridge Converters 96

1.2.6.1

Asymmetrical Cascade Two-level H-bridge Converter

with the Factor of Two 98

1.2.6.2

Asymmetrical Cascade Two-level H-bridge Converter

with the Factor of Three 99

1.2.6.3

Adjacent Switching States 100

1.2.6.4

Voltage Rating of the Switching Components 108

1.2.7

Asymmetrical Cascade Converter with Multilevel

H-bridge Converters 110

1.2.8

Conclusions 124

2. Single Inductor Multi-output DC-DC Converters

2.1

Introduction 126

2.2

Averaging Method 133

2.3

Topologies and Circuit Analysis 135

2.3.1

Multi-output Buck Converter 136

2.3.1.1.

Double-output Buck Converter Analysis with Parallel

Connected Loads 138

2.3.1.2

Double-output Buck Converter Analysis with Series

Connected Loads 146

2.3.2

Multi-output Boost Converters 154

2.3.2.1

Double-output Boost Converter Analysis with Parallel

Connected Loads 155

2.3.2.2

Double-output Boost Converter Analysis with Series

Connected Loads 164

2.3.3

Multi-output Positive Buck-Boost Converters 170

2.3.3.1

Double-output Positive Buck-Boost Converter Analysis

with Parallel Loads 174

2.3.3.2

Double-output Positive Buck-Boost Converter Analysis

with Series Loads 182

3. Analysis of Common Mode and Shaft Voltages in AC Motor

Drive Systems

3.1

Introduction 191

3.2

AC Motor Drive Systems 192

3.3

Three-phase Inverter: Leg, Phase, Line and Common

Mode Voltages 198

3.4

Common Mode Voltage Reduction with Suitable PWM

Strategy 204

3.4.1

A Three-phase Two-level Inverter Supplied with a

Three-phase Diode Rectifier 204

3.4.3

A three-phase Inverter Supplied with a Single-phase

Diode Rectifier 216

3.4.3.1

Positive Half a Cycle 218

3.4.3.2

Negative Half a Cycle 218

3.4.3.3

Common Mode Voltage Reduction Strategy 222

3.4.4

An AC-DC-AC Motor Drive 223

3.5

Modelling of Electric Motors for Shaft Voltage and

EMI Analysis 226

3.5.1

Parasitic Elements 227

3.5.2

Extraction of Parasitic Elements 233

3.5.2.1

Test 1: Input Impedance across Windings and Stator

(motor frame) to Extract C

by Removing the Rotor

235

3.5.2.2

Test 2: Impedance of Windings to Extract C

, R

and

L 239

3.5.2.3

Test 3: Input Impedance across Rotor and Stator to

Extract C

and C

240

3.5.2.4

Test 4: Input Impedance across Windings and Rotor to

Extract C

and C

242

3.5.2.5

Test 5: Input Impedance across the Phases to Extract

C

243

3.5.3

Simplification of the Model for Different Analysis

244

3.6

Calculation of Capacitive Coupling in AC Machines in

order to Reduce Shaft Voltage and Leakage Current

249

3.6.1

The Capacitive Coupling between Stator and Winding

(C

) 252

3.6.2

The Capacitive Coupling between Rotor and Stator

(C

) 253

3.6.3

The Capacitive Coupling between Rotor and Winding

(C

) 255

Chapter 1:

1.1 Symmetrical Multilevel Converters

1.1.1 Introduction

The growing attraction of high and medium power applications in utility, industrial, and renewable energy systems has increased a demand for high and medium power converters. However, due to the maximum blocking voltage rating of switches, it is troublesome to connect only one power semiconductor switch directly to high voltage. As a result, a multilevel power converter structure has been introduced as an alternative for high and medium voltage applications

.

The basic concept of power conversion in multilevel converters is based on a series connection of switching components with several lower DC voltage sources to synthesize a staircase voltage waveform. Different energy sources or storage elements such as capacitors and batteries, or renewable energy sources such as PV panels can be considered as the DC voltage sources in various multilevel converter structures.

By neglecting the ripple on the DC link capacitor, a schematic circuit of a three-phase two-level classical converter and a multilevel converter are shown in Fig.1-1, where the input DC source (Vdc) can be one of the above-mentioned sources and the

capacitor voltages [Fig.1-1 (b)] meet the following condition:

dc C C C dc C C C V V V V V V V V n n 1 2 1 1 2 1 , , , ,   (1-1)

According to different switching states, it is possible to achieve higher voltage levels at the output voltage by adding up the DC sources in comparison with the two-level converter. This issue has been demonstrated in Fig.1-2, where each step of the output voltage level in the multilevel converter is a fraction of the total DC link voltage of the two-level converter. Therefore, the voltage rate of the power components depends on the DC voltage source to which they are connected.

As seen in Fig.1-2, a two-level converter utilizes only one DC level (Vdc) in order to

create the average of reference voltage in each switching cycle, while the multilevel converter is able to synthesis stair case output voltage using several DC link voltage levels. This is closer to a sinusoidal voltage waveform.

Synthesizing a stepped output voltage allows reduction in harmonic content of voltage waveform. In regards to harmonic spectrum of the two-level and the multilevel converters illustrated in Fig.1-3, it is apparent that the peak of harmonic contents of the output voltage in the multilevel converter is significantly declined compared to the two-level converter. This results in increasing the quality of output waveform and reducing the size and cost of the output filter. The staircase output voltage can improve the quality of the output voltage and reduce the voltage stress (dv/dt) on switching components; this can remedy the problem associated with Electromagnetic Interference (EMI) problems.

Switching losses in power converters is proportional to both the switching frequency and the voltage drop across the switching components. Therefore, the multilevel converter contributes to reducing the switching loss as it operates at a lower switching frequency and the voltage level across the semiconductor is decreased. Therefore, less switching loss or better quality are the advantages of multilevel converters compared to two-level converters.

In addition to the above merits of the multilevel converter, utilizing proper modulation technique allows possible elimination of common mode voltage generated by the converter in a motor driver system. This reduces the voltage stress on the motor bearing and increases its lifetime. This issue is discussed in the following chapters.

+

Vdc

_

ia(t)

Three-phase two-level converter

van(t) N - vaN (t)+ + vbN(t) -- v cN (t) ₊ Phase a p n vbn(t) vcn(t) ib(t) ic(t) a b c (a)

Three-phase multilevel converter

N Phase a + Vdc _ 1 C V 2 C V P C V 1 n C V + + + + -ia(t) van(t) - vaN (t)+ + vbN(t) -- v cN (t) ₊ p n vbn(t) vcn(t) ib(t) ic(t) a b c (b)

Fig.1-1: Schematic diagram of a DC-AC converter (a) two-level classical converter and (b) multilevel converter

Fig.1-2: Output voltage waveform (a) two-level and (b) multilevel converter

Multilevel converters are appropriate for medium and high voltage applications. However, one of their main drawbacks is the need for a greater number of switching components; this imposes extra expense and complexity on the overall system design. Various types of multilevel converters have been proposed based on different structures of a DC link voltage to generate staircase output voltage levels. The best known multilevel topologies are diode-clamped, flying capacitor, and cascade converters. Different current and voltage control have been proposed for multilevel converters to create optimum efficiency. Although each type of multilevel

converter shares the advantages of multilevel voltage source converters, they may be suitable for a specific application according to their structures.

0 0.005 0.01 0.015 0.02 -60 -40 -20 0 20 40 60 0 100 200 300 400 0 10 20 30 40 50 60 V o lt ag e( V ) H ar m o n ic m ag n it u d e (V ) Harmonic order Time(S) (a) 0 0.005 0.01 0.015 0.02 -60 -40 -20 0 20 40 60 0 100 200 300 400 0 10 20 30 40 50 60 V o lt ag e( V ) H ar m o n ic m ag n it u d e (V )

Time(S) Harmonic order

(b)

Fig.1-3: (a) A two-level converter output voltage waveform and harmonic contents and (b) multilevel converter output voltage and harmonic contents

This chapter is dedicated to describing and discussing the operation and structure of the three main multilevel converter topologies. In the first section, the basic operation of each converter is first analyzed to provide an overview of the nature of different structures with respect to the switching states and practical operations with equal DC link voltages (

1 2

1 C ... Cn

C V V

V ); these are termed “traditional multilevel converters” or “symmetrical multilevel converters”. High-level multilevel converters are then analyzed in order to highlight the strengths and weaknesses of each configuration. In the second section, all the multilevel converters will be

analyzed with unequal DC link voltages; these converters are termed “asymmetrical multilevel converters”.

1.1.2 Diode-clamped Converter Topology

One of the multilevel converter topologies that have achieved much attention in renewable energy systems is the diode-clamped multilevel converter, also known as „Neutral-Point-Clamped multilevel converter‟. This structure was first proposed by Nabae et al. in 1980. Multilevel diode-clamped converters are widely utilized as an interface between a high DC voltage and an AC voltage in renewable energy sources in either grid connection or residential applications. A diode-clamped converter is also a common type of converter used in variable speed drives for high-power medium-voltage (2.4 kV to 13.8 kV) motors. Static Var Compensation has been presented in the literature as an alternative application for this type of converter. Basically, diode-clamped multilevel converters synthesize the small step of staircase output voltage from several series of DC capacitor voltages. Fig.1-4 (a) shows the leg structure of a three-level diode-clamped converter where the total DC link voltage is Vdc andVC₁ VC₂ Vdc/2.

The DC bus voltage is split into two voltage sources by using two DC capacitors, C1 and C2. Each capacitor is supposed to have an equal DC voltage and each voltage stress will be limited to one capacitor level through clamping diodes (Dca1 and Dca2). This structure consists of pairs of switches, (Sa1, Sa3) and (Sa2, Sa4), which work in a complementary fashion. A single-phase and three-phase structure can be formed by the paralleling of two and three converter leg structures, respectively. A converter with more output voltage levels can be constructed by adding extra DC link capacitors and a pair of switching devices for each extra level. The load current can be positive or negative because of the phase shift between its voltage and current waveforms. Therefore, based on the load power factor, in both positive and negative output voltages, the load current can be either positive or negative. In order to work in different load power factors, switches include a MOSFET or IGBT with anti parallel diodes. This switch structure allows bidirectional current flow for positive and negative load current when the switch is turned on by its gate signal. The "on"

and "off'‟ switching states of each switch are defined as “1” and “0”, respectively. If the middle point of DC link voltage is regulated at half of the total input DC source

Sa1 Sa2 Da1 Da2 C2 C1 Da3 Sa3 Da4 Sa4 Dca1 Dca2 a n 1 C V + -2 C V + -p

Fig.1-4: One leg of three-level diode-clamped converter (a) circuit diagram and (b) output voltage waveform

(Vdc/2), based on three different switching states, three voltage levels can be

synthesized at the output voltage of the leg structure of the three-level diode-clamped converter with respect to the point “n” [See Fig.1-4 (b)]. These switching states are explained in detail below.

Switching state Sa1=0, Sa2=0 in (0<t ≤t1)

In this switching state, as shown in Fig.1-5, both top switches (Sa1 and Sa2) are “off” so that their complements Sa3 and Sa4 are “on”. When the load current is positive [Fig.1-5 (a)], reverse diodes Da3 and Da4 conduct and the load current loop can be provided through the load, Da3 and Da4. However, in the negative load current [Fig.1-5 (b)], Sa3 and Sa4 conduct and the current loop consists of Sa3 and Sa4 through the load. Therefore, as shown in Fig.1-4 (a), the output voltage in 0<t ≤t1 is:

van(t)= 0 (1-2)

According to Fig.1-5, this switching state can not affect DC link capacitors, as capacitors C1 and C2 are not included in the current loop through the load.

Sa1 Sa2 Da1 Da2 C2 C1 Da3 Sa3 Da4 Sa4 Dca1 Dca2 a n 1 C V + -2 C V +

Fig.1-5: Current loop whenSa1=0, Sa2=0 (a) positive load current and (b) negative load current

Switching state Sa1=0, Sa2=1 in (t1<t ≤t2)

In this switching state, the top switch Sa1 is turned “off”, while the other switch Sa2 is “on”. Therefore, the complementary switches in this leg, Sa3 and Sa4, are “on” and “off”, respectively. As shown in Fig.1-6 (a), when the load current is positive, the switch Sa2 and the clamped diode Dca1 conduct due to the polarity of the voltage across the diode and the current direction through the switch. Therefore, the current loop which consists of C2, Dca1, and Sa2 can dischargeC2. On the other hand, for the negative load current [Fig.1-6 (b)], Dca2 and Sa3 conduct according to the voltage polarity and the current direction. The current loop in the negative load current consists of C2, Dca2, and Sa3 through the load and it can charge C2.

Assuming that the voltage ripple is negligible on the DC link capacitors ( 1 1() C C t V V and 2 2() C C t V

V ), the output voltage in this switching state (t1<t ≤t2)

is: van(t)=VC₁=Vdc/2 (1-3) Sa1 Sa2 Da1 Da2 C2 C1 Da3 Sa3 Da4 Sa4 Dca1 Dca2 a n 1 C V + -2 C V +

Fig.1-6: Current loop whenSa1=0, Sa2=1 (a) positive load current and (b) negative load current

Switching state Sa1=1, Sa2=1 in (t2<t ≤t3)

In this switching state (as shown in Fig.1-7) both top switches, Sa1 and Sa2, are “on”, so that the complementary switches, Sa3 and Sa4, are “off”. When the load current is positive, the switches Sa1 and Sa2 conduct and the current loop consists of C1, C2, Sa1 and Sa2 [Fig.1-7 (a)]. However, for the negative load current, Da1 and Da2 conduct and the current flows through C1, C2, Da1, and Da2. Therefore, according to Fig.1-7 (b), the output voltage in t2<t ≤t3 is:

Since the capacitors have been considered as the only source of the converter so far, the load current flows through DC link capacitors in this switching state and the direction of the load current may have charged or discharged the capacitors. Positive current loop can charge the DC link capacitors, while negative load current may discharge the DC link capacitors, C1 and C2. It should be mentioned that usually, in practice, battery or another kind of DC power supply is connected to the DC link capacitors. The total DC voltage does not change significantly in this switching state according to the load current direction and the capacitance value.

Sa1 Sa2 Da1 Da2 C2 C1 Da3 Sa3 Da4 Sa4 Dca1 Dca2 a n 1 C V + -2 C V + Sa1 Sa2 Da1 Da2 C2 C1 Da3 Sa3 Da4 Sa4 Dca1 Dca2 n a 1 C V + -2 C V + (a) (b)

Fig.1-7: Current loop whenSa1=1, Sa2=1 (a) positive load current and (b) negative load current

Switching state Sa1=1, Sa2=0

This switching state is not considered in a diode-clamped configuration as the output voltage in this case depends on the load current. Fig.1-8 shows the current loops for the positive and the negative load currents. In the positive load current, Sa4 is “on” and Da3 conducts due to the direction of the current. As shown in Fig.1-8 (a), in this situation, the current loop includes Da3 and Da4 through the load and van(t)=0. In the

negative load current, Da2 conducts while Sa1 is “on”. According to Fig.1-8 (b), the current loop contains Da1, Da2, and the DC link capacitors C1 and C2 through the load

in which van(t)= VC₁+ VC2 . As discussed, this switching state is not used in

diode-clamped converters as the leg voltage depends on the load current.

Three possible voltage levels in one leg of the diode-clamped converter are distinguished by the three switching states. In practice, the capacitor voltage should be balances to an equal value by using a proper PWM strategy. The capacitor voltage levels under the balance conditions should be achieved as follows:

1 C V = 2 C V =Vdc/2 (1-5)

The output voltage levels at the balanced conditions are demonstrated in Table 1-1.

Sa1 Sa2 Da1 Da2 C2 C1 Da3 Sa3 Da4 Sa4 Dca1 Dca2 n a 1 C V + -2 C V +

Fig.1-8: Current loop whenSa1=1, Sa2=0 (a) positive load current and (b) negative load current

Table 1-1 Possible switching states for one leg of the three-level diode-clamped converter

Sa1 Sa2 van(t)

1 1 Vdc

0 1 Vdc/2

1.1.2.1 Single-phase Diode-clamped Converter

A circuit diagram of a single-phase three-level diode-clamped converter is depicted in Fig.1-9. As shown, the single-phase configuration consists of two leg structures of the diode-clamped converter (Leg “a” and Leg “b”). As demonstrated, each leg has two pairs of switching components and two clamped diodes. However, both legs share the same DC link to generate output voltage levels.

Due to the fact that each leg of the converter can synthesize three different voltage levels based on different switching states, the output voltage of the single-phase converter can be derived from

vab(t)=van(t)-vbn(t) (1-6)

As an example, in the interval 0<t ≤t1 shown in Fig.1-9 (b), assuming that (Sa1=1 and Sa2=1) in leg “a” and (Sb1=0, Sb2=1) in leg “b”, then van(t)=Vdc and vbn(t)=Vdc/2,

respectively. So, the output voltage in steady state operation is vab(t)=Vdc-Vdc/2 = Vdc/2 for this switching interval. By combination of the leg switching states given in

Table 1-1, 32 possible switching states can be derived for a single-phase three-level diode-clamped converter. These nine switching states can synthesize five different voltage levels at the output voltage of the single-phase converter and are demonstrated in Fig.1-9 (b) under the balance condition when

1 C V = 2 C V =Vdc/2.

All the switching states associated with the five different voltage levels are summarized in Table 1-2. Switching states are distinguished based on the switching states of each leg of the converter. For instance, in the switching states “1101”, the first two digits are the switching states associated with leg “a”, where (Sa1=1, Sa2=1) and the last two digits are the switching states of leg “b” where (Sb1=0, Sb2=1).

The leg voltage and phase voltage waveforms of the single-phase three-level diode-clamped converter are shown in Fig.1-10. According to Table 1-2, there are some switching states which produce a same voltage level at the output voltage. These switching states are called “redundant switching states”. As presented in Table 1-2, in the single-phase three-level diode-clamped converter, (0000, 0101 and 1111) are the redundant switching states for the voltage level 0, (0100 and 1101) are the redundant switching states for the voltage level Vdc/2 and, finally, (0001and 0111)

redundant switching states can synthesize same voltage level at output voltage, they may provide different current paths through the capacitors. This issue can be used to balance the DC link capacitor voltages (

1 C V and 2 C V ) in the diode-clamped converters. This is discussed in detail later in this chapter.

Sa1 Sa2 Sb1 Sb2 Da1 Da2 Db2 Db1 C2 C1 Vdc + -Da3 Sa3 Da4 Sa4 Db3 Sb3 Db4 Sb4 Dca1 Dca2 Dcb1 Dcb2 a b n p (a) Vdc 0 Vdc/2 vab(t) t t1 t2 0 -Vdc/2 -Vdc t3 t4 t5 t6 t7 t8 (b)

Fig.1-9: Single-phase three-level diode-clamped converter (a) circuit diagram and (b) output voltage waveform

Table 1-2 Possible switching states for the single-phase three-level diode-clamped converter Switching states van(t) vbn(t) vab(t) 0000 0 0 0 0001 0 Vdc/2 -Vdc/2 0011 0 Vdc -Vdc 0100 Vdc/2 0 Vdc/2 0101 Vdc/2 Vdc/2 0 0111 Vdc/2 Vdc -Vdc/2 1100 Vdc 0 Vdc 1101 Vdc Vdc/2 Vdc/2 1111 Vdc Vdc 0 van (t ) vbn (t ) vab (t ) Time(S)

Fig.1-10: Output voltage waveforms of the single-phase three-level diode-clamped converter; (from top to bottom) leg “a” voltage (van(t)), leg “b” voltage (vbn(t)), and

Same as the analysis for the leg structure and based on the load current direction and the voltage polarity on the switching devices, different switching components are included in the current loop for each switching state. To clarify this issue in the single-phase three-level diode-clamped converter, the current loops for two different switching states are illustrated in Fig.1-11. For the positive load current directions in Fig.1-11 (a) and Fig.1-11 (c), the switching states “0100” and “1101” can discharge C2 and C1. However, the negative load current leads to charging C1 and C2 in the switching states“0100” [Fig.1-11 (b)] and “1101” [Fig.1-11 (d)].

Modulation between adjacent voltage levels at the output voltage shown in Table 1-2 needs to be obtained by only one switch change. These switching states are defined as “adjacent switching states”. Simultaneous switching of different switches is not an immense problem when there are just a few of them happening over one cycle; however, when a switching between nonadjacent switching states occurs frequently, it becomes a critical issue because it increases the switching losses. The Fig.1-12 graph demonstrates the achievement of different voltage levels in terms of the adjacent switching states in a single-phase three-level diode-clamped converter. For modulation between levels 0 and Vdc/2, all the switching state pairs [(1111 and

1101), (0101 and 1101), (0101 and 0100), and (0000 and 0100)] can be used to follow the adjacency. Also, for a modulation between levels Vdc/2 and Vdc, adjacency

occurs between the switching states (0100 and 1100) and (1101 and 1100). The same situation is true to obtain negative voltage levels.

As there is an adjacent switching state between all voltage levels, transition between different voltage levels can occur without any extra switching losses in a three-level diode-clamped converter. The redundant switching states are apparent from Fig.1-12, in the positive or the negative voltage levels. As shown, there are three different switching states in level 0 and two different switching states in both levels Vdc/2 and

-Vdc/2. These switching states may have different effects on the DC link capacitor

voltages at each particular output voltage level. This issue is clearly shown in Fig.1-11 for the switching states “0100” and “Fig.1-1101” in level Vdc/2. Therefore, when the

this capacitor [as shown in Fig.1-11 (a)], C1 is charged to compensate for this voltage drop as the DC link is normally connected to a constant DC source.

Sa1 Sa2 Sb1 Sb2 Da1 Da2 Db2 Db1 C2 C1 Vdc + -Da3 Sa3 Da4 Sa4 Db3 Sb3 Db4 Sb4 Dca1 Dca2 Dcb1 Dcb2 a _b (a) Sa1 Sa2 Sb1 Sb2 Da1 Da2 Db2 Db1 C2 C1 Vdc + -Da3 Sa3 Da4 Sa4 Db3 Sb3 Db4 Sb4 Dca1 Dca2 Dcb1 Dcb2 a _b (b)

Sa1 Sa2 Sb1 Sb2 Da1 Da2 Db2 Db1 C2 C1 Vdc + -Da3 Sa3 Da4 Sa4 Db3 Sb3 Db4 Sb4 Dca1 Dca2 Dcb1 Dcb2 a _b (c) Sa1 Sa2 Sb1 Sb2 Da1 Da2 Db2 Db1 C2 C1 Vdc + -Da3 Sa3 Da4 Sa4 Db3 Sb3 Db4 Sb4 Dca1 Dca2 Dcb1 Dcb2 a _b (d)

Fig.1-11: Current loops in the single-phase three-level converter: Switching state “0100” (a) positive (b) negative load current; Switching state “1101” (c) positive

Inversely, while C2 is charged by the negative load current in “0100”, C1 is discharged to keep the total DC link constant, as presented in Fig.1-11 (b). As shown in Fig.1-11 (c) and (d), opposite circumstances for the capacitor charging and discharging conditions occur for switching state “1101” to generate the same voltage level due to the reverse direction of the load current. This feature can be used as a freedom in the capacitor voltage balancing in diode-clamped converters.

1100 1101 0101 1111 Vdc Vdc/2 0 0000 0100 0011 0001 0111 -Vdc -Vdc/2 Adjacent switching states

Fig.1-12: Adjacent switching states in the single-phase three-level diode-clamped converter

1.1.2.2 Three-phase Three-level Diode-clamped Converter

A three-phase three-level diode-clamped converter can be assembled by connecting three leg structures of the three-level diode-clamped converter, as shown in Fig.1-13. As each leg of the converter consists of three different switching states, there are 33 different switching states in the three-phase three-level diode-clamped converter. These twenty seven different switching states can produce five different voltage levels at each line output voltage which can be defined as

vab(t)=van(t)-vbn(t)

vbc(t)=vbn(t)-vcn(t) (1-7)

All possible switching states of the three-phase three-level converter with all associated leg and line voltage levels are demonstrated in Table 1-3. It is supposed that the capacitor voltages (

1

C

V and

2

C

V ) can be controlled at Vdc/2. Similar to the

single-phase converter, the switching states are defined based on the switching states in each leg of the converter. For instance, in the switching state “110100”, the first two digits are the switching states of the leg “a” where (Sa1=1 and Sa2=1), two middle digits are allocated to switching states of the leg “b” where (Sb1=0 and Sb2=1), and the last two digits represent the switching states of the leg “c” where (Sc1=0 and Sc2=0). Sa1 Sa2 Sb1 Sb2 Sc1 Sc2 Da1 Da2 Db2 Db1 Dc1 Dc2 C2 C1 Vdc + -Da3 Sa3 Da4 Sa4 Db3 Sb3 Db4 Sb4 Dc3 Sc3 Dc4 Sc4 Dca1 Dca2 Dcb1 Dcb2 Dcc1 Dcc2 a _b c p n

Fig.1-13: Three-phase three-level diode-clamped converter

According to Table 1-3, the three-phase converter has more redundant switching states at each line voltage which can be used in the control system. Fig.1-14 shows current loops through the switches and the DC link capacitors for two redundant switching states to generate voltage levels (vab(t)=Vdc/2,vbc(t)=0,vca(t)=-Vdc/2).

Considering the direction of ia(t) as the positive load current for the phase “a”

(negative load current for the other two phases), different current loops with respect to the switching states “110101” and “010000” have different effects on the DC link capacitor voltages.

Sa1 Sa2 Sb1 Sb2 Sc1 Sc2 Da1 Da2 Db2 Db1 Dc1 Dc2 C2 C1 Vdc + -Da3 Sa3 Da4 Sa4 Db3 Sb3 Db4 Sb4 Dc3 Sc3 Dc4 Sc4 Dca1 Dca2 Dcb1 Dcb2 Dcc1 Dcc2 a _b c ia(t) ib(t) ic(t) ib(t)+ ic(t) ia(t) (a) Sa1 Sa2 Sb1 Sb2 Sc1 Sc2 Da1 Da2 Db2 Db1 Dc1 Dc2 C2 C1 Vdc + -Da3 Sa3 Da4 Sa4 Db3 Sb3 Db4 Sb4 Dc3 Sc3 Dc4 Sc4 Dca1 Dca2 Dcb1 Dcb2 Dcc1 Dcc2 a _b ia(t) _i b(t) ic(t) ib(t)+ ic(t) ia(t) (b)

Fig.1-14: Current loops in a three-phase three-level converter (a) switching state “110101” and (b) switching state “010000”

Leg voltage and phase voltage waveforms of the three-phase three-level diode-clamped converter are shown in Fig.1-15. There are three voltage levels appearing in each leg voltage of each phase. Also, five different voltage levels can be synthesized by different combinations of the three leg voltage levels to generate three-phase voltages with 120 degree phase difference.

Table 1-3 Switching states for a three-phase three-level diode-clamped converter Switching states van(t) vbn(t) vcn(t) vab(t) vbc(t) vca(t) 000000 0 0 0 0 0 0 010000 Vdc/2 0 0 Vdc/2 0 -Vdc/2 110000 Vdc 0 0 Vdc 0 -Vdc 000100 0 Vdc/2 0 -Vdc/2 Vdc/2 0 010100 Vdc/2 Vdc/2 0 0 Vdc/2 -Vdc/2 110100 Vdc Vdc/2 0 Vdc/2 Vdc/2 -Vdc 001100 0 Vdc 0 -Vdc Vdc 0 011100 Vdc/2 Vdc 0 -Vdc/2 Vdc -Vdc/2 111100 Vdc Vdc 0 0 Vdc -Vdc 000001 0 0 Vdc/2 0 -Vdc/2 Vdc/2 010001 Vdc/2 0 Vdc/2 Vdc/2 -Vdc/2 0 110001 Vdc 0 Vdc/2 Vdc -Vdc/2 -Vdc/2 000101 0 Vdc/2 Vdc/2 -Vdc/2 0 Vdc/2 010101 Vdc/2 Vdc/2 Vdc/2 0 0 0 110101 Vdc Vdc/2 Vdc/2 Vdc/2 0 -Vdc/2 001101 0 Vdc Vdc/2 -Vdc Vdc/2 Vdc/2 011101 Vdc/2 Vdc Vdc/2 -Vdc/2 Vdc/2 0 111101 Vdc Vdc Vdc/2 0 Vdc/2 -Vdc/2 000011 0 0 Vdc 0 -Vdc Vdc 010011 Vdc/2 0 Vdc Vdc/2 -Vdc Vdc/2 110011 Vdc 0 Vdc Vdc -Vdc 0 000111 0 Vdc/2 Vdc -Vdc/2 -Vdc/2 Vdc 010111 Vdc/2 Vdc/2 Vdc 0 -Vdc/2 Vdc/2 110111 Vdc Vdc/2 Vdc Vdc/2 -Vdc/2 0 001111 0 Vdc Vdc -Vdc 0 Vdc 011111 Vdc/2 Vdc Vdc -Vdc/2 0 Vdc/2 111111 Vdc Vdc Vdc 0 0 0

Leg “a” voltage (van(t)) Leg “b” voltage (vbn(t)) Leg “c” voltage (vcn(t))

Line voltage (vab(t)) Line voltage (vbc(t))

Time(S) Line voltage (vac(t)) 0 0.01 0.02 0 0.01 0.02 0 0.01 0.02 0 0.01 0.02 0 0.01 0.020 0.01 0.02 V dc V dc/2 V dc/2 V dc -V dc -V dc/2 0 0

Fig.1-15: Leg and line voltage waveforms of the three-phase three-level diode-clamped converter

1.1.2.3 Capacitor Voltage Control in Diode-clamped Converters

In diode-clamped converters, series connection of the capacitors at the DC link voltage is necessary to synthesize staircase output voltage by dividing the total input voltage into two or more different DC voltage levels. This structure is suitable for many applications such as power systems and renewable energy systems. Assuming that the DC link capacitors were large enough in the previous cases, the DC link voltages were regulated at the exact amount of /2

2 1 C dc

C V V

V by neglecting the

ripple. However, using a large capacitor at the DC side is not practical as it is too bulky and expensive. Therefore, different current loops due to different switching states may cause the capacitor voltages to be unbalanced. To clarify this issue, a capacitor current equation for (n-1) capacitors in series, is given in (1-8).

dt t dv C t iC_j j Cj ) ( ) ( (j=1, 2,…, n-1) (1-8) where i (t) j

C is the current through the jth DC link capacitor (Cj) in an n-level converter, and v (t)

j

the DC link is constant over one switching cycle, then the capacitor voltage changes linearly. Fig.1-16 demonstrates the DC link capacitor voltage regarding both positive and negative capacitor currents. (1-8) can be rewritten for the switching period as follows: t V C t t v T t v C I j j j j C j C sw C j C ) ( ) ( (1-9)

where t is the time interval of the capacitor current change (as shown in Fig.1-16) and

j

C

V is the capacitor voltage change during this interval. Thus, the variation of

the capacitor voltage in each switching period can be defined as follows:

j C C C I t V j j (1-10)

According to (1-10), the direction of the current through the capacitors can increase or decrease the voltage across the capacitors in each switching period, as shown in Fig.1-16. Therefore, controlling the current can control the capacitor voltages in the diode-clamped converter.

T

T

Fig.1-16: Capacitor voltage variation based on current direction

In diode-clamped converters, DC link capacitors are connected to load at different switching periods. Thus, these switching states may provide different current paths to charge or discharge the capacitors. The output voltage of two different cases has been shown in Fig.1-17. In Fig.1-17 (a), the DC link voltage of a three-level diode-clamped converter is constructed by a series connection of DC capacitors, while in Fig.1-17 (b), the DC link consists of a series connection of constant DC sources. By comparing these two cases, it is clear that the voltage of the middle point in the DC

link capacitors with respect to the bottom of the DC link voltage (

2

C

V ) can not be regulated at Vdc/2, as shown in Fig.1-17 (a). As shown in this figure, based on the

current direction through the capacitors, this voltage can be more or less than Vdc/2.

This unbalancing can cause some problems in the diode-clamped configuration. Since one of the capacitor voltages is more than Vdc/2 during the unbalancing period,

the voltage stress across some switches is increased. This can damage the switches. In addition, unbalanced capacitor voltage can cause harmonic distortion to the current and affect voltage waveforms which results in a reduction in the quality of the output waveforms. Therefore, the DC link capacitor voltage balancing is necessary to create the desired voltage levels at the output voltage.

0 0.005 0.01 0.015 0.02 0 0.005 0.01 0.015 0.02

V_dc

V_dc/2

0

Leg voltage with DC link capacitors Leg voltage with regulated DC sources

Time(S) Time(S)

(a) (b)

Fig.1-17: Leg voltage waveforms of a three-level diode-clamped converter (a) DC link with two series capacitors and (b) DC link with two series DC sources

To generate output voltage in multilevel converters, the duty cycle of switches can be defined based on different PWM strategies. Due to this fact, a proper switching transition is chosen by a controller to generate the desired output voltage. However, the DC link capacitor voltage unbalance problem happens due to different current loops through selected switches and capacitors. Therefore, based on the sign of load current, a DC link capacitor can be presented in a charging or discharging situation in different switching transitions. Table 1-4 shows these situations in a single-phase three-level diode-clamped converter for the positive load current.

Table 1-4 DC link capacitors charging states with respect to different switching states in a single-phase three-level diode-clamped converter

Switching states vab(t) iLoad(t)>0 C1 C2 0000 0 No change No change 0001 -Vdc/2 Discharge Charge 0011 -Vdc No change No change 0100 Vdc/2 Charge Discharge 0101 0 No change No change 0111 -Vdc/2 No change No change 1100 Vdc Discharge Discharge 1101 Vdc/2 Discharge Charge 1111 0 No change No change

As given in Table 1-4, the capacitor voltages can be controlled in some voltage levels (Vdc/2 and -Vdc/2) as there are options for charging or discharging the DC link

capacitors; however, at the voltage levels Vdc, -Vdc and 0, the capacitor voltages can

not be changed. As mentioned before, redundant switching states (0001 and 0111) in voltage level –Vdc/2 and (0100 and 1101) in voltage level Vdc/2 can help to balance

the capacitors‟ voltage due to their different effect on DC link capacitors. This issue is shown in Fig.1-18 for a three-level converter in which the total DC voltage is supplied by a constant DC source, and output voltage is Vdc/2. By assuming a

positive load current through C2 and a negative current through C1 [as shown in Fig.1-18 (a)], the load current is drawn from C2 which leads to discharging the bottom capacitor. As the total DC link voltage is constant (

1 C V + 2 C V =Vdc), a

current can be injected to the top capacitor from the DC source. As a consequence in this situation, the C2 is discharged by the load current and C1 is charged with the DC source current. The switching state “1101” in Fig.1-18 (b) can discharge C1 and charge C2, similar to the switching state”0100”. It is mentioned that in the cases when the total DC source is supplied by a diode rectifier, charging and discharging situations should be taken into account based on the fact that the rectified output

voltage and the DC link capacitor voltage may fluctuate. In general, the switching states “0011” and “1100” can charge or discharge both capacitors if they are not connected to a DC source. Sa1 Sa2 Sb1 Sb2 Da1 Da2 Db2 Db1 C2 C1 Vin Da3 Sa3 Da4 Sa4 Db3 Sb3 Db4 Sb4 Dca1 Dca2 Dcb1 Dcb2 a b + -R-L iLoad(t) ) ( 1 t iC ) ( 2 t i_C (a) Sa1 Sa2 Sb1 Sb2 Da1 Da2 Db2 Db1 C2 C1 Da3 Sa3 Da4 Sa4 Db3 Sb3 Db4 Sb4 Dca1 Dca2 Dcb1 Dcb2 a _b + -Vin R-L iLoad(t) ) ( 1 t iC ) ( 2 t i_C (b)

Fig.1-18: Current loop in a single-phase three-level converter with positive load current (a) switching state “0100” and (b) switching state “1101”

With choosing the switching states to balance the capacitors in modulation between two voltage levels, the adjacent switching states should also be taken into account to minimize the switching losses. As seen in Fig.1-19, for modulation between (0 and

Vdc/2), it is possible to either charge or discharge C1 and C2 based on their voltage error in voltage level Vdc/2 if the controller chooses “0101” as a switching state to

generate voltage level 0. For modulation between (Vdc/2 and Vdc), once the

controller selects “1100” to synthesis level Vdc, the next adjacent switching states to

produce voltage level Vdc/2 can be chosen among the switching states available in

this level. In a positive load current for instance, if the voltage of the top capacitor (

1

C

V ) is less than the bottom one (

2

C

V ), the switching state “0100” should be chosen to charge C1 and discharge C2. In contrast, the switching state “1101” should be chosen when the top and bottom capacitors should be discharged and charged, respectively. The same scenario is valid for the negative load current. Therefore, the capacitor voltage balancing using adjacent switching state is possible in different modulation levels in a single-phase three-level diode-clamped converter.

1100 1101 0101 1111 Vdc Vdc/2 0 0000 0100 Charge Discharge C1 C2 No change

Adjacent switching states

C1 C2

C1 C2

C1 C2 _C C1 C2

1 C2

Fig.1-19: DC link capacitor charging states with respect to different voltage levels and adjacent switching states in a single-phase three-level converter with positive

load current

The capacitor voltage balancing algorithm for more than three levels has some restrictions and these are discussed specifically at the end of this section.

1.1.3 Flying Capacitor Converter Topology

The flying- capacitor converter was proposed by Meynard and Foch in 1992. The structure of this converter is similar to the diode-clamped converter except that the voltage clamping is achieved by means of capacitors that float with respect to the input DC link voltage. Output voltage can be synthesized by connecting the capacitors based on different switching states. A leg structure of a three-level flying capacitor converter is shown in Fig.1-20. If the ripple on the DC capacitors is neglected, this structure includes: one DC link capacitor (C) with potential of Vdc

across it, a leg capacitor (Ca1) with VC_a1=Vdc/2 to synthesis step voltage at the

output voltage, and two pairs of switches with anti-parallel diodes to conduct positive and negative load current. A leg voltage can be synthesized by connecting the leg capacitor (Ca1) in series with the DC link capacitor (C). More voltage levels can be achieved by connecting more pair of switches and leg capacitors, and this is discussed in the following section.

Switches have the same structure as the diode-clamped converter. However, the complementary switches are constituted by (Sa1, Sa4) and (Sa2, Sa3), as shown in Fig.1-20 (a). Using this configuration, four different switching states can be utilized in each leg to obtain different voltage levels which have one more switching state than a diode-clamped converter. As seen in Fig.1-20 (b), when the voltage of Ca1 is assumed at Vdc/2 (VCa₁ Vdc/2), three different voltage levels can be synthesized at the leg voltage based on four different switching states. Operation of this configuration in different switching states is analyzed as follows:

Switching state Sa1=0, Sa2=0 in (0<t ≤t1)

In this switching state both top switches Sa1 and Sa2 are “off”, so that their complements Sa4 and Sa3 are “on”. When the load current is positive, the reverse diodes Da3 and Da4 conduct and the current loop consist of Da3, Da4 and a load. However, in a negative load current, Sa3 and Sa4 conduct and the current loop consists of Sa3, Sa4 and the load. Therefore, as shown in Fig.1-21 (a), the output voltage in interval 0<t ≤t1 is:

van(t)= 0 (1-11)

In this switching state, the leg capacitor voltage (

1

a

C

V ) is not influenced by the load current as it is not included in the current loop.

Sa1 Sa2 Da1 Da2 C + -Da3 Sa3 Da4 Sa4 a Ca1 Vdc n p

Fig.1-20: One leg of a three-level flying capacitor converter (a) circuit diagram and (b) output leg voltage waveform

Sa1 Sa2 Da1 Da2 C + -Da3 Sa3 Da4 Sa4 a Ca1 Vdc n

Fig.1-21: Current loops whenSa1=0 and Sa2=0 (a) positive load current and (b) negative load current

Switching state Sa1=0, Sa2=1 (t1<t ≤t2)

As shown in Fig.1-22 (a), for the positive load current, the switch Sa2 from the top and the anti-parallel diode Da4 from the bottom conduct due to the polarity of the voltage across the diode and the current direction through the switch. The current loop includes Ca1, Sa2, Da4, and the load. By assuming a positive load current, as shown in Fig.1-22 (a), this switching state can discharge the leg capacitor Ca1. On the other hand, for the negative load current, Da2 and Sa4 conduct according to the polarity of the voltage. This current loop can charge Ca1 based on the depicted direction. The current loop in a negative load current is shown in Fig.1-22 (b) and consists of Ca1, Da2, and Sa4. The output voltage for this switching state is:

van(t)= VCa₁ Vdc/2 (1-12) Sa1 Sa2 Da1 Da2 C + -Da3 Sa3 Da4 Sa4 a Ca1 Vdc n

Fig.1-22: Current loops whenSa1=0, Sa2=1 (a) positive load current and (b) negative load current

Switching state Sa1=1, Sa2=0 (t1<t ≤t2)

In spite of a diode-clamped structure, this switching state is one of the switching states to achieve Vdc/2. Current loops for a positive and negative load current are

conduct for the positive load current, and Da1 and Sa3 conduct for the negative load current. Here again, by considering

1

a

C

V at half of the DC link capacitor voltage, the output voltage in the subinterval t1<t ≤t2 is shown in Fig.1-20 (b) which is derived from (1-13).

van(t)=Vdc-VC_a1=Vdc/2 (1-13)

In this switching state, as the current loop is constituted through the leg capacitor (Ca1) state, the capacitor can be charged by the positive load current as shown in Fig.1-23 (a), and discharged by the negative load current as shown in Fig.1-23 (b).

Sa1 Sa2 Da1 Da2 C + -Da3 Sa3 Da4 Sa4 a Ca1 Vdc n

Fig.1-23: Current loops whenSa1=1, Sa2=0 (a) positive load current and (b) negative load current

Switching state Sa1=1, Sa2=1 in (t2<t ≤t3)

In this switching state, both top switches Sa1 and Sa2 are “on” and their complements Sa3 and Sa4 are “off”. As shown is Fig.1-24 (a), for a positive load current , the switches Sa1 and Sa2 conduct so that the current loop consists of C, Sa1 and Sa2, and the load; meanwhile, for a negative load current, Da1 and Da2 conduct, and the

current flows through C, Da1, Da2, and the load [Fig.1-24 (b)]. Therefore, the output voltage in subinterval t2<t ≤t3 is:

van(t)= VC=Vdc (1-14)

The load current flows through the DC link capacitors in this switching state so that this switching state cannot affect the leg capacitor voltage as there is no current loop through it. According to the different switching states given in Table 1-5, three possible voltage levels can be synthesized by four different switching states. It is assumed that the DC link voltage is connected to a constant voltage source Vdc, and

leg capacitor (Ca1) voltage is controlled at Vdc/2 (VC_a1=Vdc/2) by choosing proper

switching states. Sa1 Sa2 Da1 Da2 C + -Da3 Sa3 Da4 Sa4 a Ca1 Vdc n Sa1 Sa2 Da1 Da2 C + -Da3 Sa3 Da4 Sa4 Ca1 Vdc a n (a) (b)

Fig.1-24: Current loops whenSa1=1, Sa2=1 (a) positive load current and (b) negative load current

As presented in switching interval t1<t ≤t2, both of the switching states “01” and “10” generate same voltage level at Vdc/2. Therefore, there is a redundant switching

state in each leg voltage of the flying capacitor topology. The adjacent switching states are shown in Fig.1-25. The redundant switching states can guarantee the

capacitor voltage balancing with adjacency in each leg of the converter as they have different effects on the charge and discharge of the leg capacitor.

Vdc Vdc/2 0 10 01 11 00

Fig.1-25: Adjacent switching states in one leg of a three-level flying capacitor converter

Table 1-5 Switching states in one leg of the three-level flying capacitor converter Sa1 Sa2 van(t)

0 0 0

0 1 Vdc/2

1 0 Vdc/2

1 1 Vdc

1.1.3.1 Single-phase Flying Capacitor Converter

A single-phase three-level flying capacitor converter can be built with two legs (Leg “a” and Leg “b”) which are connected to the same DC link voltage, as shown in Fig.1-26. Each leg consists of two pairs of switching components and one leg capacitor. Regarding the output voltage equation of the single-phase converter given in (1-6), five different voltage levels can be generated at the output voltage of the three-level flying capacitor converter by controlling the voltage of Ca1 and Cb1. In order to have a balance condition, the voltage of the leg capacitors should be regulated at Vdc/2. The output voltage of the three-level single-phase flying capacitor

converter under the balanced condition is demonstrated in Fig.1-26 (b). Sixteen possible switching states with respect to the combination of the leg switching states can synthesize five different voltage levels in the single-phase three-level flying capacitor converter. All switching states associated with the five different voltage

levels are summarized in Table 1-6. The switching states are defined based on the switching states of each leg of the converter similar to the diode-clamped topology.

Sa1 Sa2 Sb1 Sb2 Da1 Da2 Db2 Db1 C Vdc + -Da3 Sa3 Da4 Sa4 Db3 Sb3 Db4 Sb4 a b Ca1 Cb1 n p (a) Vdc 0 Vdc/2 vab(t) t t8 0 -Vdc/2 -Vdc t1 t2 t3 t4 t5 t6 t7 (b)

Fig.1-26: A single-phase three-level flying capacitor converter (a) circuit diagram and (b) output waveform

As there are sixteen different switching states to obtain five voltage levels, it is apparent that there are more redundant switching states available in the single-phase

flying capacitor when compared to the diode-clamped converter. The graph of the switching states to achieve different voltage levels is shown in Fig.1-27.

Table 1-6 Switching states for the single-phase three-level flying capacitor converter Switching states van(t) vbn(t) vab(t) 0000 0 0 0 0001 0 Vdc/2 -Vdc/2 0010 0 Vdc/2 -Vdc/2 0011 0 Vdc -Vdc 0100 Vdc/2 0 Vdc/2 0101 Vdc/2 Vdc/2 0 0110 Vdc/2 Vdc/2 0 0111 Vdc/2 Vdc -Vdc/2 1000 Vdc/2 0 Vdc/2 1001 Vdc/2 Vdc/2 0 1010 Vdc/2 Vdc/2 0 1011 Vdc/2 Vdc -Vdc/2 1100 Vdc 0 Vdc 1101 Vdc Vdc/2 Vdc/2 1110 Vdc Vdc/2 Vdc/2 1111 Vdc Vdc 0

As shown in Fig.1-27, six redundant switching states are available at voltage level 0 and four redundant switching states are available for levels Vdc/2 and -Vdc/2.

Adjacent switching states are available between all consecutive voltage levels; this means that modulation between two consecutive voltage levels can be obtained by only one switch transition. In addition, adjacency between switching states of voltage levels 0 and Vdc/2 gives more freedom of choice in controlling the leg

capacitor voltages in the three-level flying capacitor converter. For instance, if the switching state “1010” is considered as a present state [Fig.1-28 (a)], there are two adjacent switching options such as “1000” and “1110” for modulation between levels 0 and Vdc/2. These two switching states at level Vdc/2 may provide different

current loops through the leg capacitors in leg “a” and leg “b”. Fig.1-28 (b) and (c) present the current loops in these switching states for the positive load current. The same situation is available for all other switching states at voltage level 0, so that the leg capacitor voltage balancing can be implemented based on this freedom to choose different adjacent switching states in the flying capacitor topology.

1100 1101 0101 1111 Vdc Vdc/2 0 0000 0100 Adjacent switching states 1000 1110 1010 0110 1001

(a) Positive half cycle

0101 1111 0000 0011 0001 0111 -Vdc -Vdc/2 1011 0010 1010 0110 1001 0

(b)Negative half cycle

Fig.1-27: Adjacent switching states in the single-phase three-level flying capacitor converter Sa1 Sa2 Sb1 Sb2 Da1 Da2 Db2 Db1 C Vdc + -Da3 Sa3 Da4 Sa4 Db3 Sb3 Db4 Sb4 a b Ca1 C_b1 (a)

Sa1 Sa2 Sb1 Sb2 Da1 Da2 Db2 Db1 C Vdc + -Da3 Sa3 Da4 Sa4 Db3 Sb3 Db4 Sb4 a b Ca1 C_b1 (b) Sa1 Sa2 Sb1 Sb2 Da1 Da2 Db2 Db1 C Vdc + -Da3 Sa3 Da4 Sa4 Db3 Sb3 Db4 Sb4 a b Ca1 Cb1 (c)

Fig.1-28: Current loops in a single-phase three-level flying capacitor converter, with positive load current (a) switching state “1010” (b) switching state “1110” and (c)

If the voltage across the leg capacitor in the flying capacitor converter is controlled at half of the DC link voltage, the five-level output voltage and three-level leg voltage of a single phase flying capacitor converter is similar to that shown in Fig.1-10.

1.1.3.2 Three-phase Three-level Flying Capacitor Converter

Configuration of a three-phase three-level flying capacitor converter with a three-leg structure is shown in Fig.1-29.

Based on a combination of the leg switching states, there are 43different switching states in a three-phase three-level flying capacitor topology. These sixty four switching states can synthesis five different voltage levels in each line output voltage. Table 1-7 illustrates all possible switching states of the phase three-level converter with all associated leg and line voltage three-levels when the leg capacitor voltages are controlled at Vdc/2. So, we have:

1 a C V = 1 b C V = 1 c C V =VC/2=Vdc/2 (1-15) Sa1 Sa2 Sb1 Sb2 Sc1 Sc2 Da1 Da2 Db2 Db1 Dc1 Dc2 C Vdc + -Da3 Sa3 Da4 Sa4 Db3 Sb3 Db4 Sb4 Dc3 Sc3 Dc4 Sc4 a b c Ca1 Cb1 Cc1 n p

Fig.1-29: Three-phase three-level flying capacitor converter

Similar to the three-phase diode-clamped converter, the switching states are defined based on the switching states of each leg of the converter and are categorized based on the switching states which produce the same line voltage levels shown in