Simulator for Intel x86/x64

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Simulator for Intel® x86/x64 1

Simulator for Intel® x86/x64

TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents ...  TRACE32 Instruction Set Simulators ...  Simulator for Intel® x86/x64 ... 1

TRACE32 Simulator License ... 3

Quick Start of the Simulator ... 4

Peripheral Simulation ... 6

Troubleshooting ... 6

FAQ 6 Emulation Modes ... 7

SYStem.CONFIG Configure debugger according to target topology 7 SYStem.CPU CPU type 7 SYStem.CpuAccess Run-time memory access (intrusive) 7 SYStem.LOCK Lock and tristate the debug port 8 SYStem.MemAccess Real-time memory access (non-intrusive) 8 SYStem.Mode Establish the communication with the simulator 9 General SYStem Settings and Restrictions ... 10

SYStem.Option REL Relocation register 10 SYStem.Option MEMoryMODEL Define memory model 10 Memory Classes ... 13

Support ... 14

Available Tools 14 Compilers 17 Realtime Operation System 17 3rd Party Tool Integrations 18 Products ... 19

Product Information 19

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Simulator for Intel® x86/x64

Version 24-May-2016

All general commands are described in the ”IDE Reference Guide” (ide_ref.pdf) and “General Commands Reference”.

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TRACE32 Simulator License

[build 68859 - DVD 02/2016]

The extensive use of the TRACE32 Instruction Set Simulator requires a TRACE32 Simulator License. For more information, see www.lauterbach.com/sim_license.html.

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Quick Start of the Simulator

To start the simulator, proceed as follows:

1. Select the device prompt for the ICD Debugger and reset the system.

The device prompt B:: is normally already selected in the command line. If this is not the case, enter B:: to set the correct device prompt. The RESet command is only necessary if you do not start directly after booting the TRACE32 development tool.

2. Specify the CPU specific settings.

The default values of all other option are set in such a way that it should be possible to work without modification. Please consider that this is probably not the best configuration for your target.

B::

RESet

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3. Enter debug mode.

This command resets the CPU and enters debug mode. After this command is executed it is possible to access memory and registers.

4. Load the program.

The format of the Data.LOAD command depends on the file format generated by the compiler. Refer to Supported Compilers to find the command that is necessary for your compiler.

A detailed description of the Data.LOAD command and all available options is given in the reference guide.

5. Start-up Example

A typical start sequence is shown below. This sequence can be written to a PRACTICE script file (*.cmm) and executed with the command DO <filename>.

*) These commands open windows on the screen. The window position can be specified with the

WinPOS command. SYStem.Up

Data.LOAD.format <filename> ; load program and symbols

B:: ; Select the ICD device prompt

WinCLEAR ; Clear all windows

SYStem.CPU <cpu_name> ; Select CPU type

SYStem.Up ; Reset the target and enter ; debug mode

Data.LOAD.format <filename> ; Load the application

Register.Set pc main ; Set the PC to function main

PER.view ; Show clearly arranged peripherals ; in window *)

Data.List ; Open source code window *)

Register /SpotLight ; Open register window *)

Frame.view /Locals /Caller ; Open the stack frame with ; local variables *)

Var.Watch %Spotlight flags ast ; Open watch window for ; variables *)

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Peripheral Simulation

For more information, see ”API for TRACE32 Instruction Set Simulator” (simulator_api.pdf).

Troubleshooting

FAQ

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Emulation Modes

SYStem.CONFIG

Configure debugger according to target topology

The SYStem.CONFIG commands have no effect on the simulator. They are only provided to allow the user to run PRACTICE scripts written for the debugger within the simulator without modifications.

SYStem.CPU

CPU type

Selects the processor type.

SYStem.CpuAccess

Run-time memory access (intrusive)

Default: Denied.

Format: SYStem.CPU <mode>

Format: SYStem.CpuAccess Enable | Denied | Nonstop

Enable Allow intrusive run-time memory access.

Since a non-intrusive run-time memory access (SYStem.MemoryAccess CPU) is available for all TRACE32 instruction set simulators, there is no need for an intrusive run-time memory access.

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SYStem.LOCK

Lock and tristate the debug port

Default: OFF.

If the system is locked, no access to the debug port will be performed by the debugger. While locked, the debug connector of the debugger is tristated. The main intention of the lock command is to give debug access to another tool.

The command has no effect for the simulator.

SYStem.MemAccess

Real-time memory access (non-intrusive)

.

Default: Denied.

Denied Lock intrusive run-time memory access.

Nonstop Lock all features of the debugger, that affect the run-time behavior. Nonstop reduces the functionality of the debugger to:

• run-time access to memory and variables • trace display

The debugger inhibits the following: • to stop the program execution

• all features of the debugger that are intrusive (e.g. action Spot for points, performance analysis via StopAndGo mode, conditional break-points etc.)

Format: SYStem.LOCK [ON | OFF]

Format: SYStem.MemAccess CPU | Denied<cpu_specific>

SYStem.ACCESS (deprecated)

CPU Real-time memory access during program execution to target is enabled.

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SYStem.Mode

Establish the communication with the simulator

Default: Down. Selects the target operating mode.

If the mode Go is selected, this mode will be entered, but the control button in the SYStem window jumps to the mode Up.

Format: SYStem.Mode <mode>

<mode>: Down NoDebug Go Up

Down The CPU is in reset. Debug mode is not active. Default state and state after fatal errors.

NoDebug The CPU is running. Debug mode is not active. Debug port is tristate. In this mode the target should behave as if the debugger is not connected.

Go The CPU is running. Debug mode is active. After this command the CPU can be stopped with the break command or if any break condition occurs.

Up The CPU is not in reset but halted. Debug mode is active. In this mode the CPU can be started and stopped. This is the most typical way to activate debugging.

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General SYStem Settings and Restrictions

SYStem.Option REL

Relocation register

IREL option must be set to the same value the user program write to the REL register.

The adjusted I/O base address can be read back with the functions IOBASE() and IOBASE.ADDRESS(). They return the offset or the complete address (offset and access mode) for the I/O area.

SYStem.Option MEMoryMODEL

Define memory model

Default: LARGE (Multi-Segment Model).

Selects the memory model TRACE32 uses for code and data accesses. The memory model describes how the CS (code segment), DS (data segment), SS (stack segment), ES, FS and GS segment registers are currently used by the processor.

The command SYStem.Option.MMUSPACES ON will override the setting of

SYStem.Option.MEMoryMODEL with the memory model MMUSPACES.

Format: SYStem.Option REL <value>

Format: SYStem.OptionMEMoryMODEL <model>

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The selection of the memory model affects the following areas:

• The way TRACE32 augments program or data addresses with information from the segment descriptors. Information augmented is the segment selector, offset, limit and access width. • The TRACE32 address format

• The way TRACE32 handles segments when the debugger address translation is enabled (TRANSlation.ON).

LARGE This is the default memory model. It is enabled after reset. This memory model is used if the application makes use of the six segment registers (CS, DS, ES, FS, GS, SS) and the global descriptor table (GDT) and/or the local descriptor table (LDT).

TRACE32 supports GDT and LDT descriptor table walks in this memory model. if a TRACE32 address contains a segment descriptor and the specified segment descriptor is not present in any of the six segments CS, DS, ES, FS, GS or SS, TRACE32 will perform a descriptor table walk through the GDT or the LDT to extract the descriptor information and apply it to the address.

Access classes of program and data addresses will be augmented with information from the CS and DS segments.

Segment translation is used in TRACE32 address translation. TRACE32 addresses display the segment selector to the left of the address offset. The segment selector indicates the GDT or LDT segment descriptor which is used for the address.

Example address: NP:0x0018:0x0003F000

LDT This memory model should be selected if a LDT is present and the debugger uses multiple entries from it. TRACE32 addresses contain a LDTR segment selector specifying the LDT entry which applies to an address.

Access classes of program and data addresses will be augmented with the information specified by the LDTR segment selector.

Segment translation is used in TRACE32 address translation. TRACE32 addresses display three numeric elements:

• The 16-bit LDTR segment selector used pointing to the LDT for the address

• The 16-bit CS (for program addresses) or DS (for data addresses) segment selector, extracted from the LDT

• The 16-bit address offset

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SingleLDT This memory model should be selected if a LDT is present but the debugger works with only one single LDT entry. The LDT is not used to differentiate addresses.

Access classes of program and data addresses will be augmented with information from the CS (for program addresses) or DS (for data addresses) segment.

Segment translation is used in TRACE32 address translation. TRACE32 addresses display the segment selector to the left of the address offset. Example address: NP:0x001C:0x0003F000

ProtectedFLAT This memory model is used if the segment translation and limit checks of the CS and the DS registers are required, but the segment register contents are kept constant. Consequently, TRACE32 addresses contain no segment descriptor because no descriptor table walk is used to reload the segment registers.

Access classes of addresses are not augmented with segment information.

TRACE32 addresses display only the access class and the address offset. Example address: NP:0xC0003F000

Segment translation is used in TRACE32 address translation for limit checking. Accesses to program addresses use the CS segment, accesses to data addresses use the DS segment.

FLAT This memory model is used if segmentation plays no role for an application and memory management makes use of paging only.

Segments are ignored, no segment translation is performed. Accesses to program and data addresses are treated the same.

Example address: NP:0xC0003F000

(MMUSPACES) This memory model can only be enabled with the command

SYStem.Option.MMUSPACES ON.

Memory model MMUSPACES is used if TRACE32 works with a kernel awareness and memory space identifiers (spaceIDs) are used in addresses to identify process specific address spaces.

Segments are ignored, no segment translation is performed.

TRACE32 addresses display a 16-bit memory space identifier to the left of the address offset. Example address: NP:0x29A:0xC0003F000

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Memory Classes

Memory Class Description

D Data

P Program

IO I/O

C Memory access by CPU E Emulation memory access

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Support

Available Tools

CPU IC E FIRE IC D DEB U G IC D MO NI T O R IC D TRA C E PO W E R IN TE GRA T OR IN STR U CTIO N SIMU LA T O R 230 YES YES 330 YES YES

8086 YES YES YES

8088 YES YES YES

80C186EA YES YES YES

80C186EB YES YES YES

80C186EC YES YES YES

80C186XL YES YES YES

80C188EA YES YES YES

80C188EB YES YES YES

80C188EC YES YES YES

80C188XL YES YES YES

AM186CC YES YES YES

AM186CH YES YES YES

AM186CU YES YES YES

AM186ED YES YES YES

AM186EM YES YES YES

AM186EMLV YES YES YES

AM186ER YES YES YES

AM186ES YES YES YES

AM186ESLV YES YES YES

AM188EM YES YES YES

AM188EMLV YES YES YES

AM188ER YES YES YES

AM188ES YES YES YES

AM188ESLV YES YES YES

C27XX YES YES

CE2600 YES YES

CE4200 YES YES

CE5300 YES YES

COREI3 YES YES

COREI3-2NDGEN YES YES

COREI3-3RDGEN YES YES

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COREI5 YES YES

COREI5-4THGEN YES YES

COREI7 YES YES

COREI7-4THGEN YES YES

D2500 YES YES D2550 YES YES D2700 YES YES D410 YES YES D425 YES YES D510 YES YES D525 YES YES

E382X YES YES

E620 YES YES

E620T YES YES

E640 YES YES

E640T YES YES

E645C YES YES

E645CT YES YES

E660 YES YES

E660T YES YES

E665C YES YES

E665CT YES YES

E680 YES YES

E680T YES YES

N2600 YES YES N270 YES YES N280 YES YES N2800 YES YES N450 YES YES N455 YES YES N470 YES YES N475 YES YES N550 YES YES N570 YES YES

QUARKX1000 YES YES

V20 YES YES YES

V30 YES YES YES

CPU ICE FIRE ICD DEB

U G ICD MO NI T O R ICD TR A C E PO WER IN TEGRA T OR INSTR U C T IO N SIMULA T O R

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V40 YES YES YES

V50 YES YES YES

Z2420 YES YES Z2460 YES YES Z2480 YES YES Z2520 YES YES Z2560 YES YES Z2580 YES YES Z2720 YES YES Z2760 YES YES Z2780 YES YES Z37XX YES YES Z500 YES YES Z510 YES YES Z510P YES YES Z510PT YES YES Z515 YES YES Z520 YES YES Z520PT YES YES Z530 YES YES Z530P YES YES Z540 YES YES Z550 YES YES Z560 YES YES Z600 YES YES Z615 YES YES Z625 YES YES Z650 YES YES Z670 YES YES

CPU ICE FIRE ICD DEB

U G ICD MO NI T O R ICD TR A C E PO WER IN TEGRA T OR INSTR U C T IO N SIMULA T O R

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Compilers

Realtime Operation System

Language Compiler Company Option Comment

ASM AXLS HP HP Source level

debugging C BORLANDC Borland Software

Corporation

EOMF-86 with Paradigm LOCATE

C ORGANON CAD-UL

ElectronicServices GmbH

EOMF-86 Banking support

C IC86 Intel Corporation OMF-86 C MCC86 Mentor Graphics

Corporation

EOMF-86 incl. Microtec ext. C MSC/MSVC-16BIT Microsoft Corporation EOMF-86 with Paradigm

LOCATE C MSC/MSVC Microsoft Corporation EXE/TD with Paradigm

LOCATE

C ICC86 TASKING OMF-86

C ICC86 TASKING IEEE

C++ BORLANDC Borland Software Corporation

EXE/TD C++ MSVC-16BIT Microsoft Corporation EXE/CV MODULA LOGITECH-M2 Terra Datentechnik MAP/REF PASCAL TEK-PASCAL Tektronix TEK

PLM PL/M86 Intel Corporation OMF-86 reads src or list file

Name Company Comment

ChorusOS Oracle Corporation

Nucleus PLUS Mentor Graphics Corporation

pSOS+ Wind River Systems 2.1 to 2.5, 3.0 RTXC 3.2 Quadros Systems Inc.

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3rd Party Tool Integrations

CPU Tool Company Host

ALL ADENEO Adeneo Embedded

ALL X-TOOLS / X32 blue river software GmbH Windows ALL CODEWRIGHT Borland Software

Corporation

Windows ALL CODE CONFIDENCE

TOOLS

Code Confidence Ltd Windows ALL CODE CONFIDENCE

TOOLS

Code Confidence Ltd Linux ALL EASYCODE EASYCODE GmbH Windows ALL ECLIPSE Eclipse Foundation, Inc Windows ALL RHAPSODY IN MICROC IBM Corp. Windows ALL RHAPSODY IN C++ IBM Corp. Windows ALL CHRONVIEW Inchron GmbH Windows ALL LDRA TOOL SUITE LDRA Technology, Inc. Windows ALL UML DEBUGGER LieberLieber Software

GmbH

Windows ALL ATTOL TOOLS MicroMax Inc. Windows ALL VISUAL BASIC

INTERFACE

Microsoft Corporation Windows

ALL LABVIEW NATIONAL

INSTRUMENTS Corporation

Windows

ALL CODE::BLOCKS Open Source

-ALL C++TEST Parasoft Windows

ALL RAPITIME Rapita Systems Ltd. Windows

ALL DA-C RistanCASE Windows

ALL TRACEANALYZER Symtavision GmbH Windows ALL SIMULINK The MathWorks Inc. Windows ALL TA INSPECTOR Timing Architects GmbH Windows

ALL UNDODB Undo Software Linux

ALL VECTORCAST UNIT TESTING

Vector Software Windows ALL VECTORCAST CODE

COVERAGE

Vector Software Windows ALL WINDOWS CE PLATF.

BUILDER

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Products

Product Information

Order Information

OrderNo Code Text LA-8813

SIM-86

TRACE32 Instruction Set Simulator for 0x86

TRACE32 Instruction Set Simulator for 0x86 family

Order No. Code Text