For the time being, there are 3 types of producers: a simple software generator to push data to memory without a hardware readout card, a more elaborated emulator generating data with realistic LHC clock rates and formatted data, and finally the readout class able to get data from C-RORC and CRU devices using the RoC library. As a side remark, from the driver and software point of view, each CRU x16 card is actually seen as two independent x8 devices, so Readout instantiates two RoC equipments to read out one CRU card.
1 Institute of Nuclear and Particle Physics, TU Dresden
Abstract. The design of readout electronics for the LAr calorimeters of the ATLAS detector to be operated at the future High-Luminosity LHC (HL-LHC) requires a detailed simulation of the full readout chain in order to find optimal solutions for the analog and digital processing of the detector signals. Due to the long duration of the LAr calorimeter pulses relative to the LHC bunch crossing time, out-of-time signal pileup needs to be taken into account. For this purpose, the simulation framework AREUS has been developed. It models analog-to- digital conversion, gain selection, and digital signal processing at bit precision, including digitization noise and detailed electronics eﬀects. Trigger and object reconstruction algorithms are taken into account in the optimization process.
On-board non-volatile memory for storage is provided by 3 flash chips: a 512 Mb PC28F00AP30TFA NOR chip and a 128 Mb N25Q128 QSPI chip, both connected to the Kintex, and another N25Q128 connected to the Zynq. All three memories are used to store the firmware for the FPGA, but while the Kintex only need the programming bitstream, the flash connected to the Zynq will also have to hold the Linux kernel image and filesystem including any software developed. The 128 Mb (= 16 MB) offered by the N25Q128 flash chip, while being the biggest supported on a single QSPI chip by the Zynq integrated flash controller , resulted to be barely sufficient for the current use but generally an excessive limitation, especially considering the capabilities offered by the Zynq: as shown in the diagram in fig.3.2, the Zynq PS includes two SD memory controllers, but in the current board revision the pins associated with both controllers are connected to an header. Given the advantage of having a large easily writable memory on-board, especially during software development, as a temporary solution it was decided to produce a simple expansion card adding a SD socket to connect to said header; since the logic level of the SD controller is at 1.8 V but the SD cards communicate with 3.3 V, this card also includes a level-shifter IC specific for SD cards. Future revisions of the board will most likely include this simple circuit in the main board.
sent back to DAQ software. A similar process happens for Si5344 chip configuration, where I2C master unit and I2C interface are used.
A simplified data path in the MuTRiG chip is also shown in Figure 6.4. Due to high bit rate of the serial data link, the 8b/10b encoded serial data from MuTRiG has to de-serialized by a special component on the FPGA, GTP receiver, which supports bit rate up to 3.125 gbps. Once configured correctly, the GTP receive will de-serialize the serial data stream at given bit rate. The GTP receiver will also perform clock data recovery (CDR), byte alignment, Loss-of-Sync (LOS) signal generation and 8b/10b decoding with the circuits in the GTP receiver block. The decoded 8 bit data is fed to downstream frame receiver unit to form 48 bit event words. The unused bit field are filled with zeros for short event structure. The frame counter value is prefixed to the event before sending to the downstream units. The event structure is shown in Table 6.1. The CRC information is checked for each frame in the frame receiver unit. A PRBS checker is implemented at the downstream of the frame receiver unit. If the MuTRiG data is PRBS debug data pattern, then the PRBS checker can be active to check if the PRBS pattern is correct, which is complement of the CRC check in the serial data link quality characterization. As the USB2.0 transmission is not fast enough for MuTRiG data, a pre-scaler unit is implement to store only a fraction of event data.
Figure 6: Some measurements to see the influence of the system configuration.
10 QuickUSB Latency and Throughput
Taken from the QuickUSB User Guide:
The period of time between the start of a transfer and the time that it actually occurs is the transfer latency. USB transfer latency is the result of several factors. First is the fact that the USB is a frame oriented bus and that all packets must be scheduled to a timebase of either 1ms (full speed) or 125us (Hi-Speed) 5 . Secondly, the oper- ating system generally assesses a software latency penalty when switching from user mode to kernel mode. Throughput is a measure of data transfer speed and is gener- ally expressed in megabytes per second (MB/s). Transfer latency affects throughput because it increases the amount of time a transfer takes regardless of the connection speed. However, as the data transfer size becomes larger, the transfer latency becomes a smaller fraction of the total transfer time thereby diminishing its effect. When the transfer size is small, the transfer latency will seriously degrade throughput. Therefore, for applications that require the highest throughput, transfer sizes of at least 64KB are recommended. Another way to mitigate transfer latency issues is to minimize the amount of time that the USB subsystem waits to schedule USB packets. You can ac- complish this using asynchronous function calls 6 . With asynchronous function calls, the transfer is scheduled when the function is called, but the function returns with- out waiting for the transfer to complete. Using this mechanism, one can concurrently schedule enough USB transfers to assure that the USB will not idle waiting for data to be transferred to or from your device. The simplest and most reliable technique for this is to employ multiple transfer buffers and rotate them on an as-needed basis.
Hz in der Abstands- und besser 10 nrad/ √ Hz in der Winkelmessung erfolgen.
In der vorliegenden Arbeit wird ein kompaktes optisches Auslesesystem – bestehend aus einem optomechanischen Aufbau mit zugehöriger Elektro- nik, Datenerfassung und Software – präsentiert, welches als Prototyp für die- se Abstands- und Winkelmetrologie dient. Das dafür entwickelte polarisie- rende Heterodyn-Interferometer mit räumlich getrennten Frequenzen basiert auf einem hoch-symmetrischen Design, bei dem zur optimalen Gleichtakt- Unterdrückung Mess- und Referenzarm die gleiche Polarisation und Frequenz sowie annähernd gleiche optische Pfade haben. Für die Winkelmessung wird die Methode der differentiellen Wellenfrontmessung (differential wavefront sensing, DWS) eingesetzt. Als Lichtquelle wird ein Nd:YAG Festkörper-Laser bei einer Wellenlänge von 1064 nm verwendet; die Heterodyn-Frequenzen werden mittels zweier akusto-optischer Modulatoren (AOMs) generiert.
Limited Warranty & Limitation of Liability
Each product from Fluke's Hart Scientific Division ("Hart") is warranted to be free from defects in mate- rial and workmanship under normal use and service. The warranty period is three years for the Thermom- eter Readout. The warranty period begins on the date of the shipment. Parts, product repairs, and services are warranted for 90 days. The warranty extends only to the original buyer or end-user customer of a Hart authorized reseller, and does not apply to fuses, disposable batteries or to any other product which, in Hart's opinion, has been misused, altered, neglected, or damaged by accident or abnormal conditions of operation or handling. Hart warrants that software will operate substantially in accordance with its func- tional specifications for 90 days and that it has been properly recorded on non-defective media. Hart does not warrant that software will be error free or operate without interruption. Hart does not warrant calibra- tions on Thermometer Readouts.
A parallel readout system has been developped to capture the raw data frame coming out of the APV25 readout chip of the CMS Silicon Strip Tracker detector. With about 10 mil- lion strips to readout, the data have to be zero-suppressed. Spying on the raw data is hence useful as a debugging tool for channels with faulty behaviour, as a validation tool for the zero- suppression procedure implemented in the standard readout electronics firmware, and finally as a unique way to provide measurements of the gain and noise during collisions, rather than relying on specific calibration runs. In this note, the hardware and software implementations of the spy channel readout system are described. Spy data taken in 2010 and 2011 are anal- ysed, allowing the monitoring of faulty components and the extraction of the first results on real-time calibration.
Some problems were also encountered with the FlowPlot software for controlling the flow rate. It was possible to measure the flow rate and set target flow rates in the software, but for some reason the flow controller did not respond to the setpoints.
Thus, a valve was manually adjusted to reach the target flow rates and the FlowPlot software was only used to measure the current flow rate. If this issue is resolved, the measurement process will become much faster.
4 DAQ software layer
The ProtoDUNE use-case has challenging requirements for the software layer, since it needs to operate at full data rate with trigger matching and loss-less data compression. In order to cope with the requirements, great care has been put into the implementation, with a main focus on avoiding dynamic memory allocation and memory copies of data fragments. Com- pression requirements introduce a challenge, as standard software implementations can’t keep up, even with bare minimum trigger rates. Therefore, hardware features of the CPU for re- ordering the data to be byte aligned and dedicated accelerators for compression are utilized.
Risk and Uncertainty
• 6.2.2 Readout Electronics Threat RD-06-02-02-002 Active 17-Oct-17 27-May-20
• Title: Chip run fails or radiation effects cause concern for readout at high rate and we need to do another run. Everything else is dependent on chip fabrication and performance both electrical and radiation. Chip iterations can take nearly 1 year so any failure of technical issues propagates a delay
By the launch of the War of 3039, many newly rediscovered technologies were starting to make an appearance, even if they were simply jury-rigged in the ﬁ eld. ComStar, for its own purposes that Trevena delves into in his War of 3039 treatise, unlocked its vault of hidden Star League designs and provided many of them to House Kurita. And for the ﬁ rst time in centuries, brand new machines of war started coming oﬀ production lines.
All of this laid the groundwork for the War of 3039. This is the perspective that General Caradoc attempted to convey with his Technical Readout: 3039. With the current events of the Inner Sphere, I believe this document presents an important picture of a time period that is still relevant; the War of 3039 planted the seeds that the Clan Invasion further watered, leading to the current glut of technologies that are wreaking such havoc during the Jihad. What’s more, a close examination of some of the personalities noted in this document will reveal important connections to the Jihad; threads that could be critical chinks in numerous factions’ armor.
During the second phase (beam off), the analog part is powered down, and a serial daisy-chained readout is performed.
For beam test operation, an external trigger is available, as well as an analog multiplexed readout for fine detector characterisation.