Modeling for Designing in Deep Submicron
6.5 Application to Low-Power Design
6.5.1 Rule for Slope Control
To minimize the short-circuit power consumption, this section presents a gate-sizing criterion for prop-erly controlling the input slope. Let us consider the structure depicted in Figure 6.9, where CA models a parasitic (including routing) capacitance. The main challenge here is to control the value of the input transition time value tIN, allowing the reduction of the short-circuit power dissipated by stage (i).
This can be accomplished by increasing the size of stage (i-1); however, this results in an increase of the energy required for its control (1/2◊C(i-1).VDDÂ). This means that, in the same way as for delay optimization, a trade-off must be defined between the reduction of the short-circuit energy consumption of stage (i) and the increase of the energy required to control stage 1). The optimal sizing of stage (i-1), for minimizing the total energy consumption ETOT of the structure (Figure 6.9) can be obtained from:
FIGURE 6.8 Propagation delay representation of the seven inverters of a 0.13-mm process.
TABLE 6.5 Voltage and Temperature Sensitivity of the tST Parameter, XT=1.65, d = 2.10–3
tST
Vpp (V)
1.08 1.2 1.32
Model Simul. Model Simul. Model Simul.
Temp. (∞K) 233 4.26 3.92 3.86 3.56 3.02 3.3
298 4.59 4.56 4.05 4.05 3.69 3.66
398 5.16 5.45 4.85 4.93 4.62 4.58
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6-14 Low-Power Electronics Design
(6.23) where C(k), CSC(k) represent respectively the input capacitance and the short-circuit capacitance of stage k.
In this expression, the first term represents the energy required to control stage (i-1), the second term, the energy consumption of stage (i-1), and, finally, the last term is the energy consumption of stage (i).
Assuming that the stage (i-1) is controlled in such a way that its inefficiency Ri-1 is minimized, Equation 6.23 becomes:
(6.24) where only the first term can be reduced by a specific slope control. Searching analytically for the optimal value of C(i-1) gives:
(6.25)
where A is a process dependent parameter defined by:
(6.26)
6.5.2 Application
The application of the sizing criterion (Equation 6.26) to an inverter tree is almost straightforward, processing backward from the output to the input of the tree; however, both the problems of divergence branches and of the output drivers have to be considered.
In minimizing the total power dissipated in an inverter tree, it appears that the optimal sizing of the output drivers depends strongly on the load content. For example, in optimizing the logic that drives a register or next gates, it can be considered that the output load is an active load or the sum of active and passive loads. Therefore, the sizing of the output driver has to be performed using Equation 6.25. If the output driver controls a passive load, however, no short-circuit power dissipation occurs in the load, and the driver must be sized at the minimum value satisfying the delay constraint.
The case of divergence branches presents a difficulty because the sizing criterion developed in the preceding section does not allow predicting the optimal sizing of the (i-1). The adopted solution is based on the fact that the power is an additive characteristic of the structure. To justify this approach, let us consider the structure represented in Figure 6.9.
FIGURE 6.9 An example of divergence and its equivalent structure.
A B
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Modeling for Designing in Deep Submicron Technologies 6-15
The sizing criterion (Equation 6.26) supplies the optimal value of Ci-1 only if CL1 = CL2, in which case the two inverters can be lumped in a unique inverter with an input gate capacitance equal to Ci(a) + Ci(b). In a general configuration, however, CL1 and CL2 have different values.
Nevertheless, as the short-circuit power dissipation is a decreasing function of CL, the two inverters (a) and (b) are modeled by a unique inverter (Figure 6.9b) loaded by CL=MAX(CL1,CL2) to avoid any overestimation of the short-circuit power dissipated by (a) and (b).
6.5.3 Validation
This sizing heuristic, based on the sizing criterion defined by Equation 6.25, has been applied to an inverter tree represented in the Figure 6.10. The total power dissipated in the different implementations has been obtained from SPICE simulations.
Figure 6.11 illustrates the power gain and loss values obtained when comparing the proposed sizing solution to a minimal surface implementation. Different values of the parasitic routing capacitance P are considered to illustrate the sensitivity of the result to the parasitic content of the load.
FIGURE 6.10 Representation of the inverter tree configuration used to validate the sizing criterion (Equation 6.25).
FIGURE 6.11 Gain and loss in delay, power, and area obtained on the inverter tree for different values of the parasitic capacitance P = P3,4 = P5,6.
20 fF 5 fF x1
5 fF 5 fF
x2 x3
x4 x5 x6 x7 x8
x11 x12 x13
x14 x15
x9 x10
30 fF P
P
60%
50%
40%
30%
20%
10%
0%
−10%
−15% LOSSESGains
P = 20f P = 40f P = 60f P = 120f
Active Power Total Power Delay Surface
X15 X8 X13X10 X15 X8 X13X10 X15 X8 X13X10 X15 X8 X13X10
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6-16 Low-Power Electronics Design
As shown, depending on the parasitic content of the inverter tree, the gain in power and speed is ranging from 3 to 15% and 13 to 45%, respectively.
The speed increase can be easily justified after a detailed analysis of the simulation results. For the considered example, the application of the sizing criterion increases the size of the stages X12, X5, and X3. This induces a reduction of the ramp duration applied at the input of the stage X14, X11, X9, X6, and X4 reducing their switching delays.
This ramp control allows to size noncritical paths at minimum dynamic power consumption. More-over, this sizing method improves the speed, compared with a minimum size implementation. As a result, this solution can be recommended as an initial solution to be implemented before any critical path optimization.
6.6 Conclusion
Due to the fast evolution of the CMOS process, associated to the increasing complexity of the structures to be managed, it becomes necessary to define metric for performance allowing designers to use easy but robust indicators to evaluate alternatives at all the steps of the design flow. Using an analytical model to evaluate the maximum switching current value, a simple but accurate design oriented representation of the performance of CMOS logic was obtained. Simple and closed form formula for the output transition time, the propagation delay, and the short-circuit power component were derived. Metrics to characterize the speed of the CMOS process, as well as its sensitivity to the supply voltage and the temperature were defined.
Clear evidence was given that the transition time can be used as a simple and robust indicator for evaluating the cell performance and for defining the conditions of load and control satisfying the imposed constraints. The definition of the transition time through parameters, which are characteristics of the process, the structure and the load, gives to the designer opportunity to characterize a cell library in terms of load and critical transition time, and to improve lookup table centering in the useful design space.
A new way for a continuous representation of these performances was introduced, allowing modeling of the complete load and inputting ramp sensitivity by one curve. A method to calibrate the parameters of this representation was given, which that was completely validated on a 0.13-mm process for different temperature and supply voltage conditions.
Considering the power dissipation as a critical design parameter, a sizing criterion for minimizing the switching power dissipation component has been presented. The latter has been obtained by lowering the short-circuit component through a control of the gate input transition time. Using an analytical model of the short-circuit power dissipation and of the output transition time, it has been demonstrated that a sizing condition minimizing the short-circuit component, can be defined. Application has been given to general inverter configurations in various loading conditions. Gain in power and speed as large as 15 and 45% can be obtained, with respect to minimal size implementations.
These indicators also give facilities in controlling the load and input transition time distribution in combinatorial paths, which is, at the physical level, the most efficient way to manage the speed to power trade-off for circuit optimization.
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