TSPC Latches and Flip-Flops - Single-Clock Latches and Flip-Flops

Low-Power Very Fast Dynamic Logic Circuits

8.2 Single-Clock Latches and Flip-Flops

8.2.1 TSPC Latches and Flip-Flops

The true single phase clock (TSPC) circuit technique [1,2] uses only a single clock and two to three clocked transistors in each latch without local inversion of the clock as such an inversion requires more clocked devices. The basic stages SP, PP, SN, and PN in TSPC are depicted in Figure 8.1, where the first letter represents the logic style (S for nonprecharged and P for precharged), and the second represents the type of clocked devices (P for p-type and N for n-type). Stages SP and PP are identical except the exchange of data and clock inputs, the same for stages SN and PN. Two cascaded SP stages (nontrans-parent when clock is high) or SN stages (nontrans(nontrans-parent when clock is low) become a p-type or n-type nonprecharged TSPC latch, respectively (see Figure 8.2(a)). A PP stage followed by an SP stage or a PN stage followed by an SN stage become a p-type or n-type precharged TSPC latch, respectively (see Figure FIGURE 8.1 Basic stages in TSPC. (© 2004 IEEE.)

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8.2(b)). A TSPC nonprecharged flip-flop consists of two cascaded nonprecharged latches, a p-type and an n-type, and it becomes positive triggered when the p-type is before the n-type, or negative edge-triggered otherwise. A TSPC precharged flip-flop is formed by a nonprecharged TSPC latch followed by a precharged TSPC latch in an opposite type, and it becomes positive edge-triggered when the non-precharged TSPC latch is a p-type, or negative edge-triggered otherwise. The nonnon-precharged TSPC latches and flip-flops are superior in low-power performance [3].

To reduce power consumption, it is possible to use only a single clocked transistor for each latch.

Figure 8.3 depicts such latches in p-type and n-type. They are so-called TSPC split-output latches in which the output of the first stage is split [2]. Edge triggered flip-flops can be built by cascading the split-output latches. As the number of clocked devices is at its minimum, the power spent on the clocked node is minimized. Because the clocked transistor propagates both high state and low state, however, one of the two states will not have a full swing. The clocked transistor should be properly sized when the supply voltage is low. In submicron technologies, the TSPC split-output latches can still be used due to reduced threshold voltages.

A very efficient and fast TSPC flip-flop using only nine transistors, based on a nonclassic flip-flop concept, is depicted in Figure 8.4(a), which gives an inverted data output [2]. The nonclassic flip-flop concept is illustrated in Figure 8.5(b), in comparison with the classic flip-flop concept depicted in Figure 8.5(a). A flip-flop transfers the input to the output only when the right clock edge comes and must be nontransparent otherwise. In a classic flip-flop the master and slave are completely nontransparent in its latching phase regardless the input logic states. In a nonclassic flip-flop, the master may be transparent in its latching phase for either a high or a low input, but the slave (which is in its nonlatching phase) must be nontransparent for the output of the master. In the example given in Figure 8.5(b), the master is transparent for a high input in its latching phase but the slave is nontransparent for the low output of the master although the slave is in its nonlatching phase. In such a way, the flip-flop is still nontransparent, which is exactly the case for the nine-transistor TSPC flip-flop depicted in Figure 8.4(a). The master is FIGURE 8.3 TSPC split-output latches. (© 2004 IEEE.)

∗ - minimum size (in all figures).

(A) A 9-transistor TSPC flip-flop.

(B) A flip-flop with all clocked devices connected to power or ground.

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8-4 Low-Power Electronics Design

a p-type half-latch with only an SP-stage and transparent for a high input. When the clock is high (latching phase), it gives a low output. The slave, an n-type precharged latch, however, is nontransparent for the low input after the PN stage finishes its evaluation. The condition of finishing evaluation increases the required hold time but just slightly because the evaluation of PN stage takes very short time. The speed increase, however, is significant because the p-type master latch with two SP stages is slower than the n-type precharged slave latch, and the removal of one of the two SP stages balances the delays of both latches. In the same time, the power consumption is reduced due to the removal of three transistors, especially the clocked p-transistor. A similar circuit but in a different transistor stacking order, illustrated in Figure 8.4(b), was published in 1973 [4] and its advantage in speed optimization was addressed in Huang and Rogenmoser [5].

Because all clocked devices are connected to power and ground rails, they can be sized without excessive loading to improve speed, though care must be taken for the charge sharing between nodes A and B and between nodes C and D. In another example, a nonclassic flip-flop can be built from a split-output SP stage and an n-type split-output latch (or an SN stage and a p-type split-output latch), reducing the number of total transistors to eight and the number of clocked devices to two, which is shown in Figure 8.4(c). For a high clock, the SP stage is half-transparent, but the split outputs respectively to the p- and n-transistors in the following latch stage can never make them transparent, although the latch is in its nonlatching phase. Another method using flow tables and signal transition graphs (STG) has been presented in Piguet [6] and Piguet and Zahnd [7] to design similar circuits including dynamic flip-flops, aiming at race-free (or, today, speed-independent [SI]) circuits.

To reduce the hold time of the flip-flop in Figure 8.4(a), a 10-transistor TSPC flip-flop illustrated in Figure 8.6(a) can be used [8]. Only the hold time for a low input needs to be reduced. The added nMOS transistor controlled by the precharged node signal will firstly increase the delay for a high input to a low output and secondly make the single stage master completely nontransparent (i.e., a full latch) without any additional clock or clocked device. A similar counterpart but with the single stage full latch FIGURE 8.5 Illustration of classic and nonclassic flip-flop concepts.

(A) A flip-flop with reduced hold-time. (B) A full-latch in a pipeline.

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Low-Power Very Fast Dynamic Logic Circuits 8-5

at the output is shown in Figure 8.6(b). The two circuits can be used for a TSPC double pipeline [9,10]

to improve its robustness, which will be discussed later.

In document LowPowerElectronics.pdf (Page 121-124)