Modeling for Designing in Deep Submicron
6.4 Application to a Standard Cell Library
In a standard industrial approach, timing performance verification is obtained using a tabular method.
The performance of each gate on a path, for each loading and control condition, is deduced from an interpolation between a set of predefined values. These values are determined from electrical simulations performed for a limited number of design conditions, such as load, input transition time, supply voltage value, and operating temperature. Characterizing each edge of the transition time and the propagation delay of each library cell, for typically five loading and input ramp conditions, involves 100 simulations.
Then considering the process corners, defined for three supply voltage values (Vmax, Vnom, Vmin) and three temperature values (Tmax, Tnom, Tmin), the characterization of a logic function imposes 900 simulations by drive strength of this function. This huge number of simulations just allows representing the design space with five loading and controlling conditions. Intermediate conditions must then be interpolated using a linear characteristic equation (e.g., f(tIN,CL) = AtIN + BCL + CtINCL + D). In submicron process, the transition time and the propagation delay exhibit a nonlinear variation with respect to the control and loading conditions that depends on each particular operating point imposed on the different com-binatorial paths. This nonlinear range must clearly be located in the design space to adequately choose the simulation points to be inserted in the lookup table.
A continuous representation of the timing performance of a CMOS library will be introduced in the next paragraph to define the output transition time and propagation delay sensitivities of the cells to the design space parameters, such as the load, the input transition time, the supply voltage and the temper-ature values.
6.4.1 Continuous Representation of Standard Cell Performance
While considering Equation 6.10 to Equation 6.15, it clearly appears that in the fast input range, tOUTFast
characterizes an inverter (gate) structure and its load. Considering the sensitivity of the different expres-sions to the input slope, tOUTFast can be used as an internal reference of the structure output transition time. In this condition, the following expression can be written:
(6.21)
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Copyright 2005 by CRC Press
Modeling for Designing in Deep Submicron Technologies 6-11
Normalizing the output transition time with respect to toutfallFast, used as a reference, the resulting expression only depends on the input transition time and is configuration ratio and load independent.
Similar results can be obtained for gates and the representation of propagation delay.
This is illustrated in Figure 6.4 where the output transition time variation of the complete family of inverters of a 0.25-mm library is represented. As expected, all the curves pile up on the same one, representing the output transition time sensitivity to the input transition time. The final value for each specific cell is then directly obtained from the evaluation of tOUTFast given in Equation 6.11, which contains the structure and load dependency.
6.4.2 Calibration Procedure
From the preceding equations and considering the variation displayed in Figure 6.4, it appears that the output transition time and the propagation delay of all the gates of a library can be characterized with a reduced set of electrical simulations. The calibration of the parameters can be performed as follows.
1. The tST value is obtained from the output transition tHL (falling edge) of a heavily loaded inverter (with a known configuration ratio k) controlled by a fast input ramp (tIN < tOUT).
2. R is obtained from the value of the ratio tLH/tHL.
3. For a small load, the variation of the apparent tST value determines the value of Cpar and CM. 4. In the slow input range (tIN > tOUT) at constant load, varying tIN determines the input slope
sensitivity (Equation 6.6).
5. Using the inverter as a reference, the gate parameters k and DW are directly determined from the ratio tGate/tInv.
6. Equation 6.9 completely determines the supply voltage sensitivity.
7. The temperature sensitivity parameters, XT and d, are obtained from the preceding steps realized at different temperature values.
6.4.3 Validation
The validation of this representation has been done on a 0.13-mm library. The target is to get a continuous characterization of the timing performance with a robust identification of the design space (fast, slow input control range) including the temperature and supply voltage sensitivity. Only simple gates are considered, such as Inverter with seven different drives, NAND, and NOR gates with two and three inputs and five different drives. Initially the timing performance (transition time and propagation delay) of all these elements has been characterized from electrical simulations. They are available in tables (TLF, STF) that give, for each edge of the transition time and the propagation delay of each element and for three temperature and supply voltage values, the corresponding performance for five different values of the load and the input transition time.
FIGURE 6.4 Full representation of the output transition time variation of the seven inverters of a 0.25-mm library.
0 7,0 6,0 5,0 4,0 3,0 2,0 1,0 0,0
5 10 15 20 25 30 35 40
Fo = 20 Fo = 15
Fo = 10
Fo = 5
Fo = 3 Fo = 1
τIN-HL/τ FastOUT-HL τ OUT-HL /τ OUT-HLFast
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Copyright 2005 by CRC Press
6-12 Low-Power Electronics Design
Following the procedure described in Section 6.3, the values of the technology parameters are deter-mined on the different tables, thus allowing to plot in Figure 6.5 to Figure 6.8 the variation of the transition time and the propagation delay of each logic family. As shown, the performance variation of all the elements of each family can be represented by one curve, as predicted by Equation 6.10.
FIGURE 6.5 Output transition time representation of the seven inverters of a 0.13-mm process.
FIGURE 6.6 Output transition time representation of the five NAND2 of a 0.13-mm process.
FIGURE 6.7 Output transition time representation of the five NOR2 of a 0.13-mm process.
3.5
2.5
1.5
0.5
0 5 10 15 20
τ OUT- HL
τ IN
τ FASTOUT
τFASTOUT
6 8
4
2
0
0 10 20 30 40 50
τOUT- LH
τIN
τ OUT FAST
τOUT FAST
6 10
8
4
2
0
0 20 40 60 80
τOUT-HL
τIN
τ OUT FAST
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Copyright 2005 by CRC Press
Modeling for Designing in Deep Submicron Technologies 6-13
Table 6.5 compares the tST supply voltage and temperature sensitivity calculated from Equation 6.9 and Equation 6.11 with the value deduced from the simulated values on the lookup tables. As shown, an excellent agreement is obtained between calculated and simulated values for all the considered supply voltage and temperature range. These variations can then be completely represented by (11):
(6.22)
where the different coefficients have been directly determined, following the calibration procedure given in the preceding part.