Dataflow Style Combinational Design
Section 4.11 Avoiding Combinational Loops 155 For input conditions corresponding to one buffer enabled and the other not
enabled, the output is the same as the enabled buffer’s input value. When both buffers are not enabled, the output is 'Z'. This value is represented on the waveform by a line halfway between the '0' and '1' logic levels.
Three-state Output Capability of a PLD
If some of the outputs of a PLD need to be multiplexed with outputs from other ICs, these outputs can be described in VHDL as three-state outputs. Since almost all PLDs have output pins with three-state capability, the described functionality is easily synthesized. One of the inputs to the PLD must be an enable signal to control the three-state outputs. Note that ports of a PLD described as mode out or inout (bidirectional) can be described as three-state outputs.
We will see a number of examples later in this book where the system being described in VHDL and implemented using a PLD connects to the system bus of a microprocessor. Those signals that connect to the data bus portion of the system bus must be three-state.
Internal Three-state Buffers in a PLD
If we need to implement a multiplexing operation within a design description, we might choose to describe this operation using three-state buffers. However, while PLDs have three-state buffers at their output pins, many PLDs do not have internal three-state buffers. When such a description is synthesized, the synthesizer attempts to replace the functionality implemented by the three-state buffers with a multiplexer or equivalent gate logic. Even so, some PLD manufacturers recommend that internal three-state buffers not be used in a description.
Furthermore, if we are writing descriptions of entities to be used as components in a hierarchical system, we should refrain from using three-state buffers on their outputs, unless the three-state outputs of the component entity will connect directly to outputs of the top-level entity. This is because three-state outputs from compo- nents that do not connect directly to outputs of the top-level entry become internal three-state buffers at the top level. In conclusion, it is best to use three-state buffers only when they are driving top-level bidirectional or output pins.
4 . 1 1 A V O I D I N G C O M B I N A T I O N A L L O O P S
When synthesizing a description of a combinational system, the synthesizer may issue a warning that the description contains a combinational loop. A combina- tional loop (Figure 4.11.1) is an output looped back (fed back) to one of the inputs. If we are attempting to describe a combinational system, our description must not contain any combinational loops. The existence of such a loop can lead to circuit instability.
Figure 4.11.1(a) shows the general case of a combinational loop. In the description of a complex system, it may not be obvious that such a loop exists. Fortu- nately, the synthesizer will detect the loop’s existence and issue a warning message.
In Listing 4.11.1 of the circuit in Figure 4.11.1(b), existence of a combinational loop is readily apparent.
Since port sigout is declared as mode out, it cannot be read in the architecture. Instead, signal s1 is declared and used to feed the NAND gate’s output back to one of its inputs. Signal s1 can then be assigned to sigout.
LISTING 4.11.1
Dataflow description of a NAND gate circuit containing a combinational loop. library ieee;
use ieee.std_logic_1164.all;
entity nandwfb is
port(
enable : in std_logic;
sigout : out std_logic
);
end nandwfb;
architecture dataflow of nandwfb is
signal s1: std_logic; begin s1 <= enable nand s1; sigout <= s1; end dataflow; FIGURE 4.11.1 Combinational loops. inputs outputs s1 enable sigout combinational loop (a) (b)
Problems 157 The concurrent statement:
s1 <= enable nand s1;
creates the combinational loop. In general, whenever a signal appears on both the left-hand and right-hand sides of an assignment statement, a combinational loop results. However, in a more complex description, the loop may not be so direct. That is, an output signal may be assigned to another signal, or chain of signals, where the last signal is assigned to an input.
Issues regarding simulation and instability of circuits with a combinational loop are discussed in detail in “Delta Delays and Combinational Feedback” on page 235 in Chapter 6.
P R O B L E M S
4.1 List the logical operators available for std_logic in order of their precedence. Include the not operator in your list. Where are these operators defined? Are they overloaded? Which of these operators are associative and which are not?
4.2 Write a signal assignment statement corresponding to each of the following Boolean equations:
(a) (b) (c) (d)
4.3 Write a signal assignment statement that assigns to signal x the NOR of inputs a, b, c, and d.
4.4 If a logical operation is performed on two arrays, how are the elements of the arrays matched to perform the operation? What restrictions apply to the lengths of the arrays?
4.5 Given the following entity and architecture: entity xor_vector is
port (x : in std_logic_vector(0 to 2); y : in std_logic_vector(2 downto 0); f : out std_logic_vector(2 downto 0)); end xor_vector;
architecture dataflow of xor_vector is begin
f <= x xor y; end dataflow;
write a functionally equivalent architecture, dataflow2, that separately computes each element of the output.
y = a b c⋅ ⋅ +a b c⋅ ⋅ +a b c⋅ ⋅ x = (a+b+c) a b c⋅( + + ) p = a+b c⋅
4.6 What kinds of statements make up a dataflow style architecture?
4.7 Name the basic forms of concurrent signal assignment statements. Another form of signal assignment statement is a simplified version of one of these basic forms. Name this derived form and the basic form from which it is derived.
4.8 For the design entity described below: library ieee;
use ieee.std_logic_1164.all; entity myckt is
port (a, b, c : in std_logic; w, y: out std_logic);
end myckt;
architecture dataflow of myckt is begin
w <= not a or (b and c);
y <= ((a and b) or c) or (not a and not b); end dataflow;
(a) Draw a block diagram of the system with inputs and outputs labeled.
(b) Directly translate the architecture to a gate level logic diagram of the circuit (without minimization).
4.9 The truth table that follows represents an arbitrary three-input three-output combinational function. Note that outputs f2 and f3 are actually the same function.
Write the CSOP functions for f1 and f2. For f3, which is functionally equivalent to f2, write a CSOP expression for the complement of the function and then complement the entire expression. This results in an equivalent expression that is the complement of a CSOP expression that has only three minterms.
4.10 For the truth table in Problem 2.19, write a complete VHDL design description of a design entity that accomplishes the function defined by the truth table. Inputs and outputs are type std_logic. Use selected signal assignment statements.
a b c f1 f2 f3 0 0 0 1 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 0 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 1 1
Problems 159 4.11 A 74HC10 contains three independent three-input NAND gates.
(a) Write an entity declaration for the entity triple_3, which is equivalent to a 74HC10. (b) Write an architecture body in the dataflow style for the entity triple_3. Use only
selected signal assignment statements.
4.12 A 4-bit binary value named fuel is input to a combinational system named fuel_encoder. This input value represents the quantity of fuel in a tank to a resolution of 1/16 of the tank’s maximum capacity. Four LEDs are used to display the quantity of fuel in the tank to a resolution of 1/4 of the tank’s maximum capacity. The LEDs form a vertical column. The system must output a 4-bit vector name leds to drive the LEDs. The most significant element of vector leds drives the top LED. The next most significant element drives the next LED down in the column, and so on. A 0 value for an element of leds turns its associated LED ON. Write a description of the system fuel_encoder. The architecture body must be named selected and use only selected signal assignment statements.
4.13 If x and y are type std_logic, give the results of the evaluation of the following relationships. For each case explain how the result is determined:
(a) x < y, where x = '0' and y = 'Z' (b) x >= y, where x = '0' and y = '1' (c) x > y, where x = 'Z' and y = '1'
4.14 Assuming that a and b are equal length std_logic_vectors, explain how the relationship a >= b is evaluated.
4.15 For the truth table in Problem 2.19, write a complete VHDL design description of a design entity that accomplishes the function defined by the truth table. Inputs and outputs are type std_logic. Use conditional signal assignment statements.
4.16 Rewrite Listing 4.5.2 to implement the 4-to-1 multiplexer using only a single conditional signal assignment statement. That is, do not assign an aggregate to a local signal.
4.17 A comparator has two 4-bit inputs a and b and two outputs. Output equal is asserted only if the two inputs are equal. Output cmpl is asserted only if the two inputs are the complement of each other. Write an entity declaration for the comparator. Write an architecture named selected that implements each output with a separate selected signal assignment statement. Write an alternative architecture named conditional that implements each output with a separate conditional signal assignment statement.
4.18 A demultiplexer has a 4-bit data input named datain. It also has four 4-bit data outputs named route0, route1, route2, and route3. The demultiplexer has two select inputs s1 and s0. The value of s1,s0 determines on which one of the four outputs the input data will appear. For example, if s1,s0 is 1,0, the input data will appear on route2. The three 4-bit data outputs that are not selected at any given time must be placed in their high impedance states (three-stated). (a) Write the entity declaration for the demultiplexer. Name the entity mux.
(b) Write an alternative architecture named condsa using one or more conditional signal assignment statements.
(c) Write an architecture name selectsa using one or more selected signal assignment statements.
4.19 A system named ones_count has an input that is a 3-bit vector named inp. The system’s output is a 4-bit vector named num_ones. The system’s output indicates the number of 1s in the input vector. That is, the element in the output vector that is a 1 indicates the number of 1s
in the input vector. Output num_ones(0) is a 1 if the number of ones in the inp is 0, otherwise it is 0. Output num_ones(1) is a 1 if the number of ones in the inp is 1, otherwise it is 0, and so on for the other outputs.
Write an entity declaration for ones_count. Write an architecture for ones_count named mixed. This architecture must use a separate concurrent signal assignment statement to compute each output. Output num_ones(0) must be computed by a Boolean expression assignment statement. Output num_ones(1) must be computed by a selected signal assignment statement. Output num_ones(2) must be computed by a conditional signal assignment statement. Output num_ones(3) may be computed by any of the three previous techniques.
4.20 In the description of the 4-to-2 priority encoder in Listing 4.6.1, the output is '11' when only input i0 is asserted and when no inputs are asserted. Rewrite the description to add an output named asserted, which allows these two cases to be distinguished. This output is a '1' only if one or more of the inputs is asserted.
4.21 Write a description of the 4-to-2 priority encoder in Listing 4.6.1 using a selected signal assignment. Take advantage of the vertical bar symbol ( | ) to put input combinations that produce the same output into the same list of choices. Compare your description to the one in Listing 4.6.1 in terms of conciseness and readability.
4.22 Write a description of the 4-to-2 priority encoder in Listing 4.6.1 using Boolean expression signal assignment statements. Compare your description to the one in Listing 4.6.1 in terms of conciseness and readability.
4.23 If you had to describe a priority encoder using a dataflow architecture and any kind of concurrent signal assignment statement, what choices of statements would be available to you? Which kind of concurrent signal assignment statement would be preferable and why?
4.24 Given the following truth table:
(a) Write a complete design description of the function in the truth table using a conditional signal assignment statement. Call the entity function_g. Treat the inputs as scalars in the entity declaration. Write the description so that the synthesizer can take advantage of the don’t care cases to simplify the function.
(b) Write an alternative architecture for entity function_g that uses a selected signal assignment. a b c g 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 - 1 0 1 - 1 1 0 1 1 1 1 0
Problems 161 4.25 Given the following truth table:
Write a complete VHDL design description of a design entity that accomplishes the function defined by the truth table. The inputs and outputs are std_logic type. Use a conditional signal assignment architecture that allows the synthesizer to take advantage of the don’t cares for logic reduction.
4.26 An n-bit thermometer code has n + 1 valid code words. The first code word has all its bits equal to 0s. The other n code words in sequence correspond to all the possible bit combinations with one or more consecutive bits equal to 1 starting with the least significant bit. All other bit combinations are invalid in this code. This code is called a thermometer code because if the code words are viewed as a vertical stack of bits, with the most significant bit at the top, the level of 1s rises like the mercury in a thermometer rises with temperature.
The analog comparators in a flash analog-to-digital converter (ADC) generate a thermometer code. However, it is required that the output of the ADC be a binary code. This is accomplished by including a thermometer to binary encoder on the ADC IC. The entity declaration for a thermometer to binary encoder for a 3-bit (output) ADC has a 7-bit input. Its entity declaration is:
entity therm2bin is port(
therm : in std_logic_vector(6 downto 0); -- thermometer code bin : out std_logic_vector(2 downto 0) -- binary code );
end therm2bin;
The output binary code simply indicates how many 1s there are in a valid input code. Write an architecture body named selected that uses a selected signal assignment with don’t cares to describe the system. Write an alternative architecture named conditional that uses a conditional signal assignment with don’t cares to describe the system.
4.27 A BCD-to-bargraph decoder is to be designed. Its entity declaration is: entity bcd_2_bar is
port ( bcd : in std_logic_vector (3 downto 0); bar_graph : out std_logic_vector (8 downto 0)); end bcd_2_bar; a b c x 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 - 1 1 0 - 1 1 1 1
The inputs represent a binary value between 0 and 9. There are nine outputs. Each output drives an LED. When an output is 0, its associated LED is ON. When it is 1, its associated LED is OFF. The LEDs are stacked in a vertical bar. The top LED is driven by bargraph(8) and the bottom LED is driven by bargraph(0).
When the input combination is 0000, all the LEDs are OFF. As the input is stepped from 0001 to 1001, the next higher LED turns ON in sequence, from the bottom to the top. When the input is 1001 all the LEDs are ON. As a result, the number of LEDs that are ON indicate the value of the BCD input.
Input values from 1010 to 1111 are invalid. If it were possible in an application that these numbers could actually occur as input values, you could simply leave all the LEDs ON for these input combinations. If it was known that none of these inputs would occur, the decoder’s outputs could be specified as don’t cares for these input combinations. Thus, the two different designs. (a) Write a description of the converter using a selected signal assignment. Have all outputs
1s for the six invalid input codes.
(b) Write a description of the converter using selected signal assignments. Assign all outputs don’t care values for the six invalid input codes.
(c) Write a description of the converter using a conditional signal assignment. Have all outputs 1s for the six invalid input codes.
(d) Write a description of the converter using conditional signal assignments. Assign all outputs don’t care values for the five invalid input codes.
(e) Synthesize the designs and compare the amount of logic required for each implementation.
4.28 A 74HC139 contains two 1-out-of-4 decoders in a single MSI circuit. The truth table for a single 1-out-of 4 decoder is given below.
As can be seen from the truth table, the 1-out-of-4 decoder has three inputs and four outputs. Inputs B and A select which output is asserted when the decoder is enabled. The decoder is enabled when the enable input G is a 0. Since VHDL does not allow overbars in identifiers, a common way of naming a signal that is active-low is to attach the suffix_bar to the signal name. Accordingly, you will use g_bar in your VHDL code to represent G.
(a) Write an entity declaration for the entity decode, which is a single 1-out-of-4 decoder whose truth table is given above.
(b) Write an architecture in the dataflow style for the entity decode. Use only conditional signal assignment statements.
Inputs Outputs G Select B A Y0 Y1 Y2 Y3 1 X X 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 1 1 1 1 1 0
Problems 163 4.29 Modify the BCD to seven-segment decoder in Listing 4.8.2, to create a hexadecimal to seven- segment decoder named hex_7seg. For this decoder, input dcba is interpreted as a 4-bit hexadecimal code. Output seg displays the value of the hexadecimal input on the seven- segment LED display.
4.30 Given the entity declaration for a BCD to seven-segment decoder in Listing 4.8.2, where each output that drives a segment is a '0' to turn the segment ON and a '1' to turn the segment OFF. (a) Write a design description whose architecture uses a selected signal assignment to
implement the conversion function. Specify the outputs as don’t cares for non-BCD input values, so that the synthesizer can produce the simplest logic.
(b) Write a design description whose architecture uses a table lookup to implement the conversion function. Specify the outputs as don’t cares for non-BCD input values so that the synthesizer can produce the simplest logic.
4.31 For the function specified by the truth table in Problem 4.25, write a complete description that implements the function using a table lookup. The architecture must allow the synthesizer to take advantage of the don’t care conditions in implementing the function.
4.32 Write an alternative architecture that uses table lookup to describe the BCD to seven-segment decoder of Listing 4.8.2. The architecture must allow the synthesizer to take advantage of the don’t care conditions in implementing the function.
4.33 Given the following truth table:
(a) Write a complete design description for a design entity named two_out_tt that implements the function described by the truth table above. The architecture body must use only a table lookup to implement the function. The name of the table is outputs and its type is table.
(b) Draw Karnaugh maps and determine how the synthesizer would assign 0s or 1s to the don’t care output values to synthesize minimal SOP logic for the outputs.
4.34 Design a 2421 code to BCD converter. The input to the converter is the std_logic_vector c2421 (3 downto 0). The input vector represents a 2421 code for a decimal digit between 0 and 9. The converter’s output is the std_logic_vector BCD (3 downto 0). The output vector represents the BCD code for the decimal digit indicated by the 2421 code.
a b c x y 0 0 0 1 0 0 0 1 0 - 0 1 0 1 0 0 1 1 0 - 1 0 0 0 0 1 0 1 - 1 1 1 0 0 0 1 1 1 1 1
Input values that are not valid 2421 code words are to be treated as don’t cares for invalid input combinations.
4.35 A 74LS251 is an 8-to-1 multiplexer with three-state outputs. It has eight data inputs D7 down to D0 and an enable input G. When it is enabled (G = 0), the data at the data input selected by its select inputs C, B, A appears at its Y output and the complement of this data appears at its W output. When it is not enabled, both of its outputs are in their high impedance states. (a) Write a design description of an entity ic74LS251 that uses selected signal assignment
statement(s) and is functionally equivalent to the 74LS251.
(b) Write an alternate architecture for the entity ic74LS251 that uses conditional signal