Three-State Buffers

to_integer returns the integer 2. For this input value, the assignment statement is equivalent to:

output <= reflected_tt(2);

or

output <= "11";

One way to view the hardware implementation of the table lookup process is as read- only memory (ROM). The system’s inputs are the ROM’s address inputs and the ROM’s contents are the table’s output values. For a particular input value (address) the ROM outputs the data stored at that address.

A synthesis tool may also view a table lookup in terms of ROM. A hierarchical view of the description in Listing 4.9.2 is given in Figure 4.9.1. However, when target of the synthesis is a PLD, the synthesizer does not synthesize the circuit as ROM. Instead, it implements the inferred logic in its reduced logic form.

The reduced logic created by the synthesizer is given in Figure 4.9.2. The reduced synthesized logic is:

4 . 1 0 T H R E E - S T A T E B U F F E R S

A three-state buffer (tristate buffer) has a data input and an enable input. Its enable input controls whether the three-state buffer is OFF and its output is high impedance ('Z'), or whether it is ON and its output is driven by its data input. Thus, the output of a three-state buffer can be either '0', '1', or 'Z'.

FIGURE 4.9.2

Technology dependent flattened-to-gates view of table lookup description of binary to reflected code description.

input[1:0] output[1:0] output\[1\].O output\[0\].O output_1_0.G_9.O input\[0\].O input\[1\].O [1:0] [1:0] [1] [1] [0] [0] output(1) = input(1)

A noninverting three-state buffer is represented by a triangle symbol. An inversion circle is added at the symbol’s output for an inverting three-state buffer (Figure 4.10.1). The enable input is shown connected to the side of the triangle symbol. As shown in Figure 4.10.1, some three-state buffers are enabled when their enable input is '0'

and others when it is '1'.

Describing

Three-state Output Ports in VHDL

In VHDL, the fact that an output port has three-state capability is not indicated by its mode. Instead, this capability is implied in the architecture by statements that assign values to the output. If, for one or more conditions, an output is assigned the value

'Z', then the output is a three-state output.

A VHDL description of a non-inverting three-state buffer is given in Listing 4.10.1. If the enable input en_bar is asserted, the buffer’s output is the same as its input. If the enable input is not asserted, the buffer’s output is 'Z'.

LISTING 4.10.1

Three-state buffer description. library ieee;

use ieee.std_logic_1164.all;

entity three_state_buffer is

port (

d_in, en_bar : in std_logic;

d_out: out std_logic );

end three_state_buffer;

architecture dataflow of three_state_buffer is

begin

d_out <= d_in when en_bar = '0' else 'Z';

end dataflow;

FIGURE 4.10.1

Section 4.10 Three-State Buffers 153

Multiplexing Two Data Sources

Multiplexing signals from two data sources using three-state buffers is achieved by connecting the two three-state buffers’ outputs together to drive the shared signal, Figure 4.10.2. While this figure represents the three-state buffers as separate logic elements, they could be integrated into the outputs of two more functionally complex systems.

When the type of connection in Figure 4.10.2 is made, the designer must add logic that controls the three-state buffers’ enable inputs so that only one or none of the buffers is enabled at a time. If only one buffer is enabled, that output determines the logic level for the shared signal. If none of the buffers is enabled, both outputs are in their high impedance states and the shared signal they drive has the high impedance value.

Bus Contention The prohibited situation, where two or more three-state outputs connected to a shared signal are simultaneously enabled, creates a serious problem if one of the enabled outputs is trying to drive the shared signal to '1' and another is trying to drive it to '0'. The resulting voltage level is in the forbidden region. This situation is referred to as bus contention. In std_logic terms, the shared signal’s value is 'X'

(forcing unknown). In a hardware implementation, excessive current may flow between the two enabled three-state outputs under this condition.

The resolution function for std_logic properly models three-state outputs driving a shared signal. In Table 3.4.2, if both outputs (drivers) are 'Z', the shared output is

'Z'. If one output is 'Z' and the other is '1', the result is '1'. If one output is 'Z'

and the other is '0', the result is '0'. If both outputs are enabled and drive different values, '0' and '1' or '1' and '0', the output is 'X'.

A structural description of the circuit in Figure 4.10.2 is given in Listing 4.10.2. The description assumes that the three-state buffer entity from Listing 4.10.1 has been compiled to the library three_state_buffer.

Waveforms from the simulation of this description are presented in Figure 4.10.3. The input stimulus just counts through all possible binary input combinations. The first input combination has the data input to each buffer equal to '0' and both FIGURE 4.10.2

Connecting the outputs of two three-state buffers to accomplish multiplexing.

d_a d_bus u1 u2 d_b en_a en_b

LISTING 4.10.2

Two three-state buffers with their outputs connected. library ieee;

use ieee.std_logic_1164.all;

library three_state_buffer; -- library containing three-state buffer

use three_state_buffer.all;

entity three_state_bus is

port (

d_a: in std_logic; -- data input buffer a

en_a_bar: in std_logic; -- enable input buffer a

d_b: in std_logic; -- data input buffer b

en_b_bar: in std_logic; -- enable input buffer b

d_bus: out std_logic -- bused data output

);

end three_state_bus;

architecture three_state_bus of three_state_bus is

begin

u1: entity three_state_buffer port map (d_a, en_a_bar, d_bus);

u2: entity three_state_buffer port map (d_b, en_b_bar, d_bus);

end three_state_bus;

enables are asserted. This corresponds to an invalid situation because the two buffers should not be enabled simultaneously. However, the output is a valid '0' because both buffers’ data inputs are '0'.

For the second input combination, indicated by the cursor, the input data at buffer

u1 is a '1' and at buffer u2 is '0', and both buffers are enabled. The output for this case is 'X', because one buffer is trying to drive the output to a '1' and the other is trying to drive it to a '0'. On the output waveform, the times during which the output is forcing an unknown value ('X') are represented by two lines, one at the '1' logic level and the other at the '0' logic level.

FIGURE 4.10.3

Section 4.11 Avoiding Combinational Loops 155