In digital systems, the logic signals that transfer information from one component to another, and from one system to another, are voltages that vary in a discrete fashion with respect to time and are carried by wires. In VHDL, signals play a similar and equally important role. Local signals connect components within an architecture to form a larger system. Port signals provide a system’s interface to its environment.
All signals in VHDL have a declared type. A signal’s type determines the set of values it can take and the operations that can be performed on those values.
Every signal must be declared before it is used. Where a signal is declared deter- mines where in the source code text it can be used—its scope or visibility. A signal can only be referenced by statements that appear within the scope of its declaration. Constants are also introduced in this chapter. A constant is a named object that is assigned a value when it is declared. Once a constant is assigned a value, its value cannot be changed. Use of constants make a description more readable and easier to modify.
3 . 1
O B J E C T C L A S S E S A N D O B J E C T T Y P E S
Signals belong to a class of VHDL language elements called objects. An object is a named item that has a value of a specified type. To place the study of signals and constants in context, this section presents an overview of objects and types.
Object Classes An object’s class represents the nature of the object and how it is used, for example, whether the object’s value can be modified and whether it has a time element
Section 3.1 Object Classes and Object Types 83 associated with it. Conventional programming languages typically have three classes of objects: constants, variables, and files. In contrast, VHDL has four:
• Signal: an object with a current value and projected (future) values. The projected values can be changed, as many times as desired, using signal assignment statements.
• Constant: an object whose value cannot be changed after it is initially specified.
• Variable: an object with only a current value. A variable’s value can be changed, as many times as desired, using variable assignment statements. • File: an object that consists of a sequence of values of a specified type. Signals, constants, and variables are synthesizable and are used in design descrip- tions. Files are not synthesizable; they are used mostly in testbenches.
Object Types Each VHDL object must be of some type. An object’s type defines the set of values the object can assume and the set of operations that can be performed on those values.
There are five types:
• Scalar type: has a single indivisible value, which can be either numeric or enumerated.
• Composite type: consists of a collection of elements each with a value. There are two kinds of composite types: arrays and records. All elements in an array are of the same type. Elements in a record can be of different types.
• Access type: provides access to objects of a given type, similar to a pointer in conventional programming languages.
• File type: provides access to objects containing a sequence of values of a given type (such as disk files). The value of a file type is the sequence of values contained in the host system file.
• Protected type: provides atomic and exclusive access to variables accessible to multiple processes (global variables).
Only scalar and composite types are synthesizable.
Strong Typing VHDL is a strongly typed language with strictly enforced type rules. If we mix different types in an expression or exceed a type’s range of values, the compiler or simulator generates an error message. For example, the integer value 0, the real number 0.0, and the bit value '0' are not the same type, and, therefore, are not the same. VHDL’s strong typing makes it easier for a compiler to detect errors.
Object Declarations
All objects must be declared before being used. A declaration introduces the name of an object, defines its type, and, optionally, assigns an initial value.
This chapter focuses on signal and constant objects of scalar and composite types. Neither signals nor constants are allowed to be of access type.
3 . 2
S I G N A L O B J E C T S
As seen in Chapter 2, the ports of a design entity are signals. From the viewpoint of a design entity, its ports can be thought of as external signals, which are simply referred to as ports. Signals within a design entity can be thought of as local or internal signals, which are simply referred to as signals.
Scope and Visibility
For each signal declared, VHDL language rules define a certain region of text, called scope or namespace, where the signal’s name can be used. A signal is said to be visible (accessible) within its scope. Outside of its scope, a signal is unknown. Any attempt to use a signal outside of its scope causes a compilation error.
A signal’s scope is determined by where it is declared. A signal can be declared in the declarative part of an entity declaration, the declarative part of an architecture body, or in a package declaration.
Port Visibility A port’s name is visible in the entity declaration in which it is declared and in any architecture bodies associated with that entity declaration. A component declaration in the declarative part of an architecture makes that component’s port signals visible in that architecture.
Signal Visibility A signal declared in the declarative part of an architecture body can only be used within that architecture; it is not visible outside of that architecture.
Information Hiding
Once a design entity’s functionality has been verified, the details of its internal operation are not subsequently of concern to a user of the design entity. This is consistent with the concept of information hiding. Therefore, it is appropriate that a signal declared in the declarative part of an architecture body not be visible outside of that architecture.