Bistable components such as latches and flip-flops are basic building blocks of any sequential circuit.
They are used to implement the memory block of Fig.4.3and to synchronize the circuit operations with an external clock signal (Sect.4.2).
Table 4.1 Robot control
circuit: next state table Current state Input:OB Next state
SAR 0 SAR
SAR 1 SRL
SRR 0 SAR
SRR 1 SRR
SAL 0 SAL
SAL 1 SRR
SRL 0 SAL
SRL 1 SRL
Table 4.2 Robot control circuit: output table Current state Outputs:RR RL
SAR 00
SRR 10
SAL 00
SRL 01
4.4.1 1-Bit Memory
A simple 1-bit memory is shown in Fig.4.11a. It consists of two interconnected inverters. This circuit has two stable states. In Fig.4.11bthe first inverter input is equal to 0 so that the second inverter input is equal to 1 and its output is equal to 0. Thus this is a stable state. Similarly another stable state is shown in Fig.4.11c. This circuit has the capacity to store a 1-bit data. It remains to define the way a particular stable state can be defined.
To control the state of the 1-bit memory, the circuit of Fig.4.11ais completed with two tristate buffers controlled by an externalLoad signal (Fig.4.12a):
• IfLoad¼ 1 then the circuit of Fig. 4.12a is equivalent to the circuit of Fig.4.12b: the input D value (0 or 1) is transmitted to the first inverter input, so that the output P is equal to NOT(D) and Q¼ NOT(P) ¼ D; on the other hand the output of the second inverter is disconnected from the first inverter input (buffer 2 in stateZ, Sect.2.4.3).
• If Load¼ 0 then the circuit of Fig. 4.12a is equivalent to the circuits of Fig. 4.12c and of Fig.4.11a; thus it has two stable states; the value ofQ is equal to the value of D just before the transition of signalLoad from 1 to 0.
Observe that the two tristate buffers of Fig.4.12aimplement the same function as a 1-bit MUX2-1.
The circuit of Fig.4.12ais a D-type latch. It has two inputs: a data inputD and a control input Load (sometimes calledEnable). It has two outputs: Q and P¼ Q. Its symbol is shown in Fig.4.13. Its working can be summarized as follows: when Load¼ 1 the value of D is sampled, and when Load¼ 0 this sampled value remains internally stored.
0
Formally, a D-type latch could be defined as a sequential circuit with an external input D, an external outputQ (plus an additional output Q), and two internal states S0andS1. The next state table and the output table are shown in Table4.3.
However this circuit is not synchronized by an external clock signal; it is a so-called asynchronous sequential circuit. In fact, the external inputLoad could be considered as a clock signal input: the value ofD is read and stored on each 1–0 (falling edge) of the Load signal so that the working of a D-type latch could be described by the equationQΔ¼ D. Nevertheless, when Load ¼ 1 then Q ¼ D (transparent state) and any change ofD immediately causes the same change on Q, without any type of external synchronization.
Another way to control the internal state of the 1-bit memory of Fig. 4.11a is to replace the inverters by 2-input NAND or NOT gates. As an example, the circuit of Fig.4.14ais an SR latch. It works as follows:
• If S¼ R ¼ 0 then both NOR gates are equivalent to inverters (Fig. 4.14b) and the circuit of Fig.4.14ais equivalent to a 1-bit memory (Fig.4.11a).
• IfS ¼ 1 and R ¼ 0 then the output of the first NOR is equal to 0, whatever the other input value, and the second NOR is equivalent to an inverter (Fig.4.14c); thusQ¼ 1.
• IfS¼ 0 and R ¼ 1 then the output of the second NOR is equal to 0, whatever the other input value, and the first NOR is equivalent to an inverter (Fig.4.14d); thusQ¼ 0.
To summarize, withS¼ 1 and R ¼ 0 the latch is set to 1; with S ¼ 0 and R ¼ 1 the latch is reset to 0; withS ¼ R ¼ 0 the latch stores the latest written value. The combination S ¼ R ¼ 1 is not used (not allowed). The symbol of an SR latch is shown in Fig.4.15.
Table 4.3 Next state table and output table of a D-type latch
Current state Load D Next state Output
S0 0 – S0 0
S0 1 0 S0 0
S0 1 1 S1 0
S1 0 – S1 1
S1 1 0 S0 1
S1 1 1 S1 1
S
R Q
Q
Q
Q 0
1 0
1
a. b. c. d.
Fig. 4.14 SR latch
Q S
R Q
Fig. 4.15 Symbol of an SR latch
An SR latch is an asynchronous sequential circuit. Its state can only change on a rising edge of eitherS or R, and the new state is defined by the following equation: QΔ¼ S þ R Q.
4.4.2 Latches and Flip-Flops
Consider again the sequential circuit of Fig.4.3. The following question has not yet been answered:
How the memory block is implemented? It has two functions: it stores the internal state and it synchronizes the operations by periodically updating the internal state under the control of a clock signal. In Sect.4.4.1a 1-bit memory component has been described, namely the D-type latch. A first option is shown in Fig.4.16.
In Fig. 4.16 the memory block is made up of m D-type latches. The clock signal is used to periodically load new values within thism-bit memory. However, this circuit would generally not work correctly. The problem is that whenclock¼ 1 all latches are in transparent mode so that after a rising edge ofclock the new values of q0,q1,. . ., qm1could modify the values ofq0Δ,q1Δ,. . ., qm1Δ
beforeclock goes back to 0. To work correctly the clock pulses should be shorter than the minimum propagation time of the combinational circuit. For that reason another type of 1-bit memory element has been developed.
A D-type flip-flop is a 1-bit memory element whose state can only change on a positive edge of its clock input. A possible implementation and its symbol are shown in Fig.4.17. It consists of two D-type latches controlled byclock and NOT(clock), respectively, so that they are never in transparent
combinational
mode at the same time. Whenclock¼ 0 the first latch is in transparent mode so that q1¼ d and the second latch stores the latest read value ofq1. Whenclock¼ 1 the first latch stores the latest read value ofd and the second latch is in transparent mode so that q¼ q1. Thus, the stateq of the second latch is updated on the positive edge ofclock.
Example 4.6 Compare the circuits of Fig. 4.18a, c: with the same input signals Load and D (Fig.4.18b, d) the output signalsQ are different. In the first case (Fig.4.18b), the latch transmits the value ofD to Q as long as Load¼ 1. In the second case (Fig.4.18d) the flip-flop transmits the value ofD to Q on the positive edges of Load.
Flip-flops need more transistors than latches. As an example the flip-flop of Fig.4.17contains two latches. But circuits using flip-flops are much more reliable: the circuit of Fig.4.19works correctly even if the clock pulses are much longer than the combinational circuit propagation time; the only
D Q
Fig. 4.18 Latch vs. flip-flop
timing condition is that the clock period must be greater than the combinational circuit propagation time. For that reason flip-flops are the memory components that are used to implement the memory block of sequential circuits.
Comment 4.2
D-type flip-flops can be defined as synchronized sequential circuits whose equation is
QΔ¼ D: ð4:5aÞ
Other types of flip-flops have been developed: SR flip-flop, JK flip-flop, and T flip-flop. Their equations are
QΔ¼ S þ R Q; ð4:5bÞ
QΔ¼ J Q þ K Q; ð4:5cÞ
QΔ¼ T Q þ T Q: ð4:5dÞ
Flip-flops are synchronous sequential circuits. Thus, (4.5a–4.5d) define the new internal stateQΔthat will substitute the current value ofQ on an active edge (positive or negative depending on the flip-flop type) ofclock. Inputs D, S, R, J, K, and T are sometimes called synchronous inputs because their values are only taken into account on active edges ofclock. Some components also have asynchro-nous inputs. The symbol of a D-type flip-flop with asynchroasynchro-nous inputsset and reset is shown in Fig.4.20a. As long asset¼ reset ¼ 0, it works as a synchronous circuit so that its state Q only changes on an active edge ofclock according to (4.5a). However, if at some momentset¼ 1 then, independently of the values of clock and D, Q is immediately set to 1, and if at some moment reset¼ 1 then, independently of the values of clock and D, Q is immediately reset to 0. An example of chronogram is shown in Fig.4.20b. Observe that the asynchronous inputs have an immediate effect onQ and have priority with respect to clock and D.