4.6 Sequential Components
4.6.2 Counters
Counters constitute another family of commonly used sequential components. Anm-state counter (or modm counter) is a Moore sequential circuit without external input and with an n-bit output q that is also its internal state and represents a natural belonging to the set {0, 1,. . ., m 1}. At each clock pulse the internal state is increased or decreased. Thus the next state equation is
qΔ¼ q þ 1ð Þ mod m up counterð Þ or qΔ¼ q 1ð Þmod m down counterð Þ: ð4:11Þ Thus counters generate cyclic sequences of states. In the case of a modm up counter the generated sequence is. . . 0 1 . . . m 2 m 1 0 1 . . . .
Definitions 4.1
• Ann-bit binary up counter has m ¼ 2nstates encoded according to the binary numeration system.
Ifn¼ 3 it generates the following sequence: 000 001 010 011 100 101 110 111 000 001 . . . .
• An n-bit binary down counter has m¼ 2n states encoded according to the binary numeration system. Ifn¼ 3 it generates the following sequence: 000 111 110 101 100 011 010 001 000 111 . . . .
• A binary coded decimal (BCD) up counter has ten states encoded according to the binary numeration system (BCD code). It generates the following sequence: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000 0001. . . . A BCD down counter is defined in a similar way.
D Q
in(t) in(t-1) in(t-2) in(t-3) in(t-4) in(t-5)
clock
out
Fig. 4.33 Detection of sequence 100101
D Q
• Ann-bit Gray counter has m¼ 2nstates encoded in such a way that two successive states differ in only one position (one bit). For example, withn ¼ 3, a Gray counter sequence is 000 010 110 100 101 111 011 001 000 010. . . .
• Bidirectional counters have a control input U/D (up/down) that defines the counting direction (up or down).
The general structure of a counter is a direct consequence of its definition. Ifm is an n-bit number, then anm-state up counter consists of an n-bit register that stores the internal state q and of a modulo m adder that computes (q + 1) mod m. In Fig.4.35aa 1-operand adder (also called half adder) with a carry inputcyINis used. The carry input can be used as an enable (EN) control input:
qΔ¼ EN q þ 1½ð Þmod m þ EN q: ð4:12Þ The corresponding symbol is shown in Fig.4.35b.
Ifm¼ 2nthen the modm adder of Fig.4.35acan be implemented by the circuit of Fig.4.36that consists ofn 1-bit half adders. Each of them computes
qiΔ ¼ qi cyi,cyiþ1 ¼ qi cyi: ð4:13Þ Observe that cyOUT could be used to enable another counter so as to generate a 2n-bit counter (22n¼ m2states) with twon-bit counters.
Example 4.7 According to (4.13) withcy0¼ cyIN¼ 1 the equations of a 3-bit up counter are q0Δ¼ q0 1 ¼ q0,q1Δ¼ q1 q0,q2Δ¼ q2 q1 q0;
to which corresponds the circuit of Fig.4.37.
Apart fromreset and EN (Fig.4.35) other control inputs can be defined, for exampleOE (output enable) as in the case of parallel registers (Fig.4.26). An additional state outputTC (terminal count) can also be defined: it is equal to 1 if, and only if, the current stateq ¼ m 1. This signal is used to interconnect counters in series. Ifm¼ 2nthen (Figs.4.36and4.37)TC¼ cyOUT.
(q + cyIN) mod m
Fig. 4.35 n-Bit up counter
qn-1 Fig. 4.36 n-Bit half adder
Example 4.8 In Fig.4.38an active-lowOE control input and a TC output are added to the counter of Fig.4.37.TC¼ 1 when q ¼ 7 (q2¼ q1¼ q0¼ 1).
To implement a bidirectional (up/down) counter, the adder of Fig.4.35is replaced by an adder-subtractor (Fig. 4.39a). An U/D (up/down) control input permits to choose between addition (U/D¼ 0) and subtraction (U/D ¼ 1). Input b_cINis an incoming carry or borrow that can be used to enable the counter. Thus
q2 q1 q0
Fig. 4.37 3-Bit up counter
q2 q1 q0 Fig. 4.38 3-Bit up counter TC
with active-lowOE and
Fig. 4.39 Bidirectional n- U/D bit counter
4.6 Sequential Components 103
qΔ¼ EN U=D q þ 1½ð Þ mod m þ EN U=D q 1½ð Þmod m þ EN q: ð4:14Þ The corresponding symbol is shown in Fig.4.39b.
As an example, the state transition graph of Fig.4.40defines a 3-bit bidirectional counter without EN control input (b_cIN¼ 1).
In some applications it is necessary to define counters whose internal state can be loaded from an external input. Examples of applications are programmable timers and microprocessor program counters. An example of programmable counter with parallel load is shown in Fig.4.41a. Ann-bit MUX2-1 permits to write into the state register eitherqΔor an external inputin. If load¼ 0 it works as an up counter, and whenload¼ 1 the next internal state is in. Thus
qΔ¼ EN load q þ 1½ð Þmod m þ EN load in þ EN q: ð4:15Þ The corresponding symbol is shown in Fig.4.41b.
Comment 4.3
Control inputsreset and load permit to change the normal counter sequence:
• If the counter is made up of flip-flops withset and reset inputs, an external reset command can change the internal state to any value (depending on the connection of the externalreset signal to
000
Fig. 4.41 Counter with parallel load
individual flip-flop set or reset inputs), but always the same value, and this operation is asynchronous.
• Theload command permits to change the internal state to any value defined by the external input in, and this operation is synchronous.
In Fig.4.42a counter with both asynchronous and synchronous reset is shown: thereset control input sets the internal state to 0 in an asynchronous way while thesynch_reset input sets the internal state to 0 in a synchronous way.
Some typical applications using counters are now described. A first application is the implemen-tation of timers. Consider an example: Synthesize a circuit with a 1-bit output z that generates a positive pulse onz every 5 s. Assume that a 1 kHz oscillator is available. The circuit is shown in Fig.4.43. It consists of the oscillator and of a mod 5000 counter with state outputTC (terminal count).
The oscillator period is equal to 1 ms. Thus a mod 5000 counter generates aTC pulse every 5000 ms that is 5 s.
A second application is the implementation of systems that count events. As an example a circuit that counts the number of 1s in a binary sequence is shown in Fig.4.44a. It is assumed that the binary sequence is synchronized by aclock signal. This circuit is an up counter controlled by the same clock signal. The binary sequence is inputted to theEN control input and the counter output gives the number of 1s within the input sequence. Every time that a 1 is inputted, the counter is enabled and one unit is added tonumber. An example is shown in Fig.4.44b.
n-bit programmable
Fig. 4.44 Number of 1’s counter
4.6 Sequential Components 105
The 1-bit counter of Fig.4.45ais a frequency divider. On each positive edge ofin, connected to the clock input, the current value ofout¼ Q is replaced by its inverse Q (Fig.4.45b). Thus,out is a square wave whose frequency is half the frequency of the inputin frequency.
A last example of application is the implementation of circuits that generate predefined sequences.
For example, to implement a circuit that repeatedly generates the sequence 10010101 a 3-bit mod 8 counter and a combinational circuit that computes a 3-variable switching functionout1are used (Fig.4.46a). Functionout1(Table4.8) associates a bit of the desired output sequence to each counter state. Another example is given in Fig.4.46band Table 4.8. This circuit repeatedly generates the sequence 100101. It consists of a mod 6 counter and a combinational circuit that computes a 3-variable switching functionout2(Table4.8).
The mod 6 counter of Fig. 4.46bcan be synthesized as shown in Fig. 4.35awith m¼ 6 and cyIN¼ 1. The combinational circuit that computes (q + 1) mod 6 is defined by the following truth table (Table4.9) and can be synthesized using the methods proposed in Chap.2.
D Q
in Q
out reset
reset in
out
a.
b.
Fig. 4.45 Frequency divider by 2
mod 8 counter reset
clock
combinational circuit 1 q
out1
mod 6 counter
combinational circuit 2 q reset
clock
a. b.
out2 Fig. 4.46 Sequence
generators
Table 4.8 Truth tables
ofout1andout2 q out1 out2
000 1 1
001 0 0
010 0 0
011 1 1
100 0 0
101 1 1
110 0 –
111 1 –