Memories

Memories are essential components of any digital system. They have the capacity to store a large number of data. Functionally they are equivalent to a set of registers that can be accessed individually, either to write a new data or to read a previously stored data.

4.6.3.1 Types of Memories

A generic memory structure is shown in Fig.4.47. It is an array of small cells; each of them stores a bit. This array is logically organized as a set of rows, where each row stores a word. In the example of Fig.4.47there are four words and each of them has six bits. The selection of a particular word, either to read or to write, is done by the address inputs. In this example, to select a word among four words, two bitsa1 anda0connected to an address bus are used. An address decoder generates the row selection signals (the word lines). For example, ifa1a0¼ 10 (2 in decimal) then word number 2 is selected. On the other hand, the bidirectional (input/output) data are connected to the bit lines. Thus, if word number 2 is selected by the address inputs, thend5is connected to bit number 5 of word number 2,d4is connected to bit number 4 of word number 2, and so on. A control inputR/W (read/

write) defines the operation, for example write ifR/W¼ 0 and read if R/W ¼ 1.

Table 4.9 Mod 6 addition q q^Δ

A list of the main types of memories is given in Fig. 4.48. A first classification criterion is volatility: volatile memories lose their contents when the power supply is turned off while nonvolatile memories do not. Within nonvolatile memories there are read-only memories (ROM) and read/write memories. ROM are programmed either at manufacturing time (mask programmable ROM) or by the user but only one time (OTP¼ one-time programmable ROM). Other nonvolatile memories can be programmed several times by the user: erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memories (a block-oriented EEPROM).

Volatile memories can be read and written. They are called random access memories (RAM) because the access time to a particular stored data does not depend on the particular location of the data (as a matter of fact a ROM has the same characteristic). There are two families: static RAM (SRAM) and dynamic RAM (DRAM).

The diagram of Fig.4.49shows different types of commercial memories classified according to their storage permanence (the maximum time without loss of information) and their ability to be programmed. Some memories can be programmed within the system to which they are connected (for example a printed circuit board); others must be programmed outside the system using a device called memory programmer. Observe also that EPROM, EEPROM, and flash memories can be reprogrammed a large number of times (thousands) but not an infinite number of times. With regard to the time necessary to write a data, SRAM and DRAM are much faster than nonvolatile memories.

Nonvolatile RAM (NVRAM) is a battery-powered SRAM.

Volatile Non-volatile

Read/Write Read/Write under Read only special conditions

Fig. 4.49 Commercial memory types

An ideal memory should have storage permanence equal to its lifetime, with the ability to be loaded as many times as necessary during its lifetime. The extreme cases are, on the one hand, mask programmable ROM that have the largest storage permanence but no reprogramming possibility and, on the other hand, static and dynamic RAM that have full programming ability.

4.6.3.2 Random Access Memories

RAMs are volatile memories. They lose their contents when the power supply is turned off. Their structure is the general one of Fig.4.47. Under the control of theR/W control input, read and write operations can be executed: if the address busa ¼ i and R/W ¼ 1 then the data stored in word number i is transmitted to the data bus d; if the address bus a¼ i and R/W ¼ 0 then the current value of bus d is stored in word number i. Consider a RAM with n address bits that store m-bit words (in Fig.4.47 n¼ 2 and m ¼ 6). Its behavior is defined by the following piece of program:

i¼ conv(a);

if R/W¼ 0 then d ¼ word(i); else word(i) ¼ d; end if;

in which conv is a conversion function that translates an n-bit vector (an address) to a natural belonging to the interval 0 to 2ⁿ 1 (this is the function of the address decoder of Fig.4.47) and word is a vector of 2ⁿm-bit vectors (an array).

A typical SRAM cell is shown in Fig.4.50. It consists of a D-type latch, some additional control gates, and a tristate buffer. The word line is an output of the address decoder and the bit line is connected to the data bus through the read/write circuitry (Fig.4.47). When the word line is equal to 1 andR/W¼ 0 then the load input is equal to 1, the tristate output buffer is in high impedance (state Z, disconnected) and the value of the bit line connected to D is stored within the latch. When the word line is equal to 1 andR/W¼ 1 then the load input is equal to 0 and the value of Q is transmitted to the bit line through the tristate buffer.

Modern SRAM chips have a capacity of up to 64 megabits. Their read time is between 10 and 100 nanoseconds, depending on their size. Their power consumption is smaller than the power consumption of DRAM chips.

An example of very simple dynamic RAM (DRAM) cell is shown in Fig.4.51a. It is made up of a very small capacitor and a transistor used as a switch. When the word line is selected, the cell capacitor is connected to the bit line through the transistor. In the case of a write operation, the bit line is connected to an external data input and the electrical charge stored in the cell capacitor is proportional to the input logic level (0 or 1). This electrical charge constitutes the stored information.

However this information must be periodically refreshed because, in the contrary case, it would be

word line

D Q Q

bit line

R/W

load Fig. 4.50 SRAM cell

4.6 Sequential Components 109

quickly lost due to the leakage currents. In the case of a read operation, the bit line is connected to a data output. The problem is that the cell capacitor is much smaller than the bit line equivalent capacitor, so that when connecting the cell capacitor to the bit line, the stored electrical charge practically disappears. Thus, the read operation is destructive. Some additional electronic circuitry is used to sense the very small voltage variations on the bit line when a read operation is executed:

before the connection of the bit line to a cell capacitor, it is pre-charged with an intermediate value (between levels 0 and 1); then an analog comparator is used to sense the very small voltage variation on the bit line in order to decide whether the stored information was 0 or 1 (Fig.4.51b). Once the stored information has been read (and thus destroyed) it is rewritten into the original memory location. The data bus interface of Fig.4.51cincludes the analog comparators (one per bit line) as well as the logic circuitry in charge of rewriting the read data. To refresh the memory contents, all memory locations are periodically read (and thus rewritten).

Modern DRAM chips have a capacity of up to 2 gigabits that is a much larger capacity than SRAM chips. On the other hand they are slower than SRAM and have higher power consumption.

4.6.3.3 Read-Only Memories

Within ROM a distinction must be done between mask programmable ROM whose contents are programmed at manufacturing time and programmable ROM (PROM) that can be programmed by the user, but only one time. Other names are one-time programmable (OTP) or write-once memories.

Their logic structure (Fig.4.52) is also an array of cells. Each cell may connect, or not, a word line to a bit line. In the case of a mask programmable ROM the programming consists in drawing some of the word-line-to-bit-line connections in the mask that corresponds to one of the metal levels (Sect.

7.1). In the case of a user programmable ROM, all connections are initially enabled and some of them can be disabled by the user (fuse technologies) or none of them is previously enabled and some of them can be enabled by the user (anti-fuse technologies).

4.6.3.4 Reprogrammable ROM

Reprogrammable ROMs are user programmable ROM whose contents can be reprogrammed several times. Their logic structure is the same as that of non-reprogrammable ROMs but the word-line-to-bit-line connections are floating-gate transistors instead of metal connections.

There are three types of reprogrammable ROM:

• EPROM: Their contents are erased by exposing the chip to ultraviolet (UV) radiation; for that, the chip must be removed from the system (for example the printed circuit board) in which it is used;

the chip package must have a window to let the UV light reach the floating-gate transistors; an external programmer is used to (re)program the memory.

bit line

word line a.

bit line

R/W pre-charge +

comparison

d_i

Read/Write circuitry + refresh

Bus de datos

R/W

b.

c.

Fig. 4.51 DRAM cell

• EEPROM: Their contents are selectively erased, one word at a time, using a specific higher voltage; the chip must not be removed from the system; the (re)programming circuitry is included within the chip.

• Flash memories: This is an EEPROM-type memory with better performance; in particular, block operations instead of one-word-at-a-time operations are performed; they are used in many applications, for example pen drives, memory cards, solid-state drives, and many others.

4.6.3.5 Example of Memory Bank

Memory banks implement large memories with memory chips whose capacity is smaller than the desired capacity. As an example, consider the implementation of the memory of Fig.4.53awith a capacity of 1 kB (1024 words, 8 bits per word) using for that the memory chip of Fig.4.53bthat can store 256 4-bit words. Thus, eight memory chips must be used (1024 8 ¼ (256  4)  8).

Leta9a8a7. . . a0be the address bits of the memory (Fig.4.53a) to be implemented. The 1024-word addressing space is decomposed into four blocks of 256 1024-words, using for that bitsa9anda8. Each block of 256 words is implemented with two chips working in parallel (Fig.4.54). To select one of the four blocks theOE (output enable) control inputs are used:

address decoder

OE0¼ OE4¼ a9 a8, OE1¼ OE5 ¼ a9 a8,

OE2¼ OE6¼ a9 a8 ,OE0¼ OE4¼ a9 a9: ð4:16Þ The complete memory bank is shown in Fig.4.55. A 2-to-4 address decoder generates the eight output enable functions (4.16).

More information about memories can be found in classical books such as Weste and Harris (2010) or Rabaey et al. (2003).

7 6 5 4 Fig. 4.54 Address space bits

256 x 4