Consider the vehicle access control system of Fig.4.1. It consists of
• A gate that can be raised and lowered by a motor
• A push button to request the access
• Two sensors that detect two particular gate positions (upper and lower)
• A sensor that detects the presence of a vehicle within the gate area The motor control system has four binary input signals:
• Request equal to 1 when there is an entrance request (push button)
• Lower equal to 1 when the gate has been completely lowered
• Upper equal to 1 when the gate has been completely raised
• Vehicle equal to 1 if there is a vehicle within the gate area The binary output signalson/off and up/down control the motor:
• To raise the gateon/off¼ 1 and up/down ¼ 1
• To lower the gateon/off¼ 1 and up/down ¼ 0
• To maintain the gate open or closedon/off¼ 0
The motor control system cannot be implemented by a combinational circuit. As an example, if at some timerequest¼ 0, vehicle ¼ 0, upper ¼ 0, and lower ¼ 0, this set of input signal values could
# Springer International Publishing Switzerland 2017
J.-P. Deschamps et al.,Digital Systems, DOI 10.1007/978-3-319-41198-9_4
79
correspond to two different situations: (1) a vehicle is present in front of the gate, the request button has been pushed and released, and the gate is moving up, or (2) a vehicle has got in and the gate is moving down. In the first caseon/off ¼ 1 and up/down ¼ 1; in the second case on/off ¼ 1 and up/
down¼ 0.
In conclusion, the values of the signals that control the motor depend on the following sequence of events:
1. Wait forrequest¼ 1 (entrance request) 2. Raise the gate
3. Wait forupper¼ 1 (gate completely open) 4. Wait forvehicle¼ 0 (gate area cleared) 5. Lower the gate
6. Wait forlower¼ 1 (gate completely closed)
A new entrance request is not attended until this sequence of events is completed.
Conclusion: Some type of memory is necessary in order to store the current step number (1–6) within the sequence of events.
4.2 Definition
Sequential circuits are digital systems with memory. They implement systems whose output signal values depend on the input signal values at timest (the current time), t 1, t 2, and so on (the precise meaning of t 1, t 2, etc. will be defined later). Two simple examples are sequence detectors and sequence generators.
Example 4.1 (Sequence Detector) Implement a circuit (Fig.4.2a) with a decimal inputx and a binary outputy. It generates an output value y ¼ 1 every time that the four latest inputted values were 1 5 5 7. It is described by the following instruction in whicht stands for the current time:
if x(t-3)¼ 1 AND x(t-2) ¼ 5 AND x(t-2) ¼ 5 AND x(t)¼ 7 then y ¼ 1; else y ¼ 0; end if;
motor request
gate area
request vehicle upper lower
ON/OFF motor
control UP/DOWN
Fig. 4.1 Vehicle access control
Thus, the corresponding circuit must store x(t 3), x(t 2), and x(t 1) and generates y in function of the stored values and of the current value ofx.
Example 4.2 (Sequence Generator) Implement a circuit (Fig. 4.2b) with a binary output y that continuously generates the output sequence 011011011011 . It is described by the following instruction in whicht stands for the current time:
if y(t-2)¼ 1 AND y(t-1) ¼ 1 then y ¼ 0; else y ¼ 1; end if;
The corresponding circuit must storey(t 2) and y(t 1) and generates the current value of y in function of the stored values. Initially (t¼ 0) the stored values y(2) and y(1) are equal to 1 so that the first output value ofy is 0.
The general structure of a sequential circuit is shown in Fig.4.3. It consists of
• A combinational circuit that implementsk + m switching functions y0,y1,. . ., yk1,q0Δ,q1Δ,. . ., qm1Δofn + m variables x0,x1,. . ., xn1,q0,q1,. . ., qm1
• A memory that stores anm-bit vector
The combinational circuit inputsx0,x1,. . ., xn1are inputs of the sequential circuit while (q0,q1, . . ., qm1) is anm-bit vector read from the memory. The combinational circuit outputs y0,y1,. . ., yk1
are outputs of the sequential circuit while (q0Δ,q1Δ,. . ., qm1Δ) is an m-bit vector written to the memory. The way the memory is implemented and the moments when the memory contents (q0,q1, . . ., qm1) are updated and replaced by (q0Δ,q1Δ,. . ., qm1Δ) will be defined later.
With this structure, the output signalsy0,y1,. . ., yk1depend not only on the current value of the input signalsx0,x1,. . ., xn1but also on the memory contentsq0,q1,. . ., qm1. The values ofq0,q1, . . ., qm1are updated at time . . . t1, t, t + 1, . . . with new values q0Δ,q1Δ, . . ., qm1Δ that are generated by the combinational circuit.
The following terminology is commonly used:
• x0,x1,. . ., xn1are theexternal inputs
• (q0,q1,. . ., qm1) is theinternal state
• (q0Δ,q1Δ,. . ., qm1Δ) is thenext state To summarize,
• The memory stores the internal state.
• The combinational circuit computes the value of the external outputs and the next state in function of the external inputs and of the current internal state.
• The internal state is updated at every time unit. . . t 1, t, t + 1, . . . by replacing q0byq0Δ,q1by q1Δ, and so on.
Example 4.3 (Sequence Detector Implementation) The sequence detector of Example4.1can be implemented by the sequential circuit of Fig.4.4in whichx, q0,q1,q2,q0Δ,q1Δ, andq2Δare 4-bit vectors that represent decimal digits. The memory must store the three previous values ofx that are q0¼ x(t 1), q1¼ x(t 2), and q2¼ x(t 3). For that
q0Δ¼ x, q1Δ¼ q0,q2Δ¼ q1: ð4:1Þ The outputy is defined as follows:
y ¼ 1 if, and only if, q2 ¼ 1 AND q1¼ 5 AND q0¼ 5 AND x ¼ 7: ð4:2Þ Equations4.1and4.2define the combinational circuit function.
In the previous definitions and examples the concept of current timet is used but it has not been explicitly defined. To synchronize a sequential circuit and to give sense to the concept of current time and, in particular, to define the moments when the internal state is updated, a clock signal must be generated. It is a square wave signal (Fig.4.5) with periodT. The positive edges of this clock signal define the times that have been called. . . t 1, t, t + 1, . . . and are expressed in multiples of the clock signal periodT. In particular the positive edges define the moments when the internal state is replaced by the next state. In Fig.4.5some commonly used terms are defined.
• Positive edge: a transition of the clock signal from 0 to 1
• Negative edge: a transition of the clock signal from 1 to 0
• Cycle: section of a clock signal that corresponds to one period
• Frequency: the number of cycles per second (1/T )
• Positive pulse: the part of a clock signal cycle whereclock¼ 1
• Negative pulse: the part of a clock signal cycle whereclock¼ 0
x y
q0Δ
q1Δ
q2Δ q0
q1
q2
combinational circuit
mem.
Fig. 4.4 Sequence detector implementation
Comment 4.1
Instead of using the positive edges of the clock signal to synchronize the circuit operations, the negative edges could be used. This is an essential part of the specification of a sequential circuit:
positive edge triggered or negative edge triggered.