=οΏ½πππππΊπΊ_ππππππ β πππππΊπΊ_πΆπΆπΆπΆπππππΆπΆπππππππππΏπΏ_πππππΏπΏπππποΏ½ + οΏ½(πΆπΆππππππππππ ππππ ππππππππππππππππ πππππππππ‘π‘ππ) Γ οΏ½πππππΊπΊ_πΆπΆππππ β πππππΊπΊ_πΆπΆπΆπΆπππππΆπΆπππππππππΏπΏ_πππππΏπΏπππποΏ½οΏ½
πππΊπΊπΆπΆππ_πΊπΊπΏπΏππ
Note: The capture elapsed time calculation is only valid after the capture event occurs, and the timer stores the captured count in the TMRn_PWM register.
Maxim Integrated Page 125 of 201
12.9 Compare Mode (5)
In compare mode, the timer peripheral increments continually, allowing the timer to be a programmable 32-bit
programmable period timer. The end of the timer period event occurs when the timer value matches the compare value, but the timer continues to increment until the count reaches 0xFFFF FFFF. The timer counter then rolls over and continues counting from 0x0000 0000.
Figure 12-5: Compare Mode Diagram
TMRn_CTRL0.en_a
β’β’β’
0x0000 0000 0x0000 0001
TMRn_INTFL.irq_a
β’β’β’
TIMER CLOCK fCN T_CLK
TMRn_CMP.compare
SOFTWARE CLEARS TMRn_INTFL.irq β’β’β’
0xFFFF FFFF
β’β’β’ β’β’β’
0x0000 0002
β’β’β’
TMRn_CNT.count
β’β’β’
β’β’β’
β’β’β’
β’β’β’
TIMER OUTPUT SIGNAL
TMRn_CTRL0.pol_a = 0 TMRn_CTRL0.pol_a = 1
TIMER OUTPUT COMPLEMENT SIGNAL (When available)
TMRn_CTRL0.pol = 0 TMRn_CTRL0.pol = 1
ο
ο
This examples uses the following configuration in addition to the settings shown above:
TMRn_CTRL1.cascade = 1 (32-bit Cascade Timer) TMRn_CTRL0.mode_a = 5 (Compare)
ο TMRn_CNT.count defaults to 0x00000000 on a timer reset. TMRn_CNT.count reloads to 0x00000001 for all following timer periods.
12.9.1 Compare Mode Timer Period
The timer period ends on the timer clock following TMRn_CNT = TMRn_CMP.
The timer peripheral automatically performs the following actions at the end of the timer period:
1. The timer remains enabled and continues incrementing. Unlike other modes, TMRn_CNT is set to 0x0000 0000 at the end of the timer period.
2. If the timer output is enabled, then the timer pin toggles state (low to high or high to low).
3. The timer interrupt bit TMRn_INTR.irq_clr is set.
a. An interrupt is generated if enabled.
12.9.2 Compare Mode Configuration
Configure the timer for compare mode by doing the following:
1. Set TMRn_CN.ten = 0 to disable the timer.
2. Set TMRn_CN.tmode to 5 to select compare mode.
3. Set TMRn_CN.pres3:TMRn_CN.pres to set the prescaler that determines the timer frequency.
4. If using the timer pin:
a. Configure the pin for the timer output alternate function and configure the electrical characteristics as needed.
b. Set TMRn_CN.tpol to match the desired (inactive) state.
5. If using the timer interrupt, enable the interrupt and set the interrupt priority.
6. Write the initial value to TMRn_CNT. This affects only the first period as the counter increments continuously, rolling over to 0x0000 0000 and continuing.
7. Write the compare value to TMRn_CMP.
8. Set TMRn_CN.ten = 1 to enable the timer.
The compare mode timer period is calculated using Equation 12-10.
Equation 12-10: Compare Mode Timer Period
πΆπΆπππππ π ππππππ ππππππππ π π ππππππππππ ππππ ππππππππππππππ = πππππΊπΊ_πΆπΆππππ β πππππΊπΊ_πΆπΆπΆπΆπππππΆπΆπππππππππΏπΏ_πππππΏπΏππππ+ 1 πππΊπΊπΆπΆππ_πΊπΊπΏπΏππ (π»π»ππ)
Maxim Integrated Page 127 of 201
12.10 Gated Mode (6)
Gated mode is similar to continuous mode, except that TMRn_CNT only increments when the timer pin is in its active state.
Figure 12-6: Gated Mode Diagram
TMRn_CN.ten
TMRn_CNT
0x0000_0000**
0x0000_0001*
TMRn_INTR.irq_clr
β’β’β’
TIMER CLOCK
TMRn_CMP
* TMRn_CNT automatically reloads with 0x0000_0001 at the end of the timer period, but software can write any initial value to TMRn_CNT before the timer is enabled.
** The default value of TMRn_CNT for the first period after a system reset is 0x0000_0000 unless changed by software.
TMRn_CN.tpol = 1 TMRn_CN.tpol = 0 TIMER PIN
(INPUT)
0x0000_0002
SOFTWARE CLEARS BIT β’β’β’
β’β’β’
β’β’β’
β’β’β’
β’β’β’
12.10.1 Gated Mode Timer Period
The timer period ends when TMRn_CNT = TMRn_CMP and the timer automatically performs the following actions:
1. TMRn_CNT is reset to 0x0000 0001. The timer remains enabled and continues incrementing.
2. The timer interrupt bit TMRn_INTR.irq_clr is set.
a. An interrupt is generated if enabled.
12.10.2 Gated Mode Configuration
Configure the timer for gated mode by performing the following:
1. Set TMRn_CN.ten = 0 to disable the timer.
2. Set TMRn_CN.tmode to 6 to select gated mode.
3. Set TMRn_CN.pres3:TMRn_CN.pres to set the prescaler that determines the timer frequency.
4. Configure the timer pin:
a. Configure the pin as a timer input and configure the electrical characteristics as needed.
b. Set TMRn_CN.tpol to match the desired initial (inactive) state.
5. If using the timer interrupt, enable the interrupt and set the interrupt priority.
6. Write an initial value to TMRn_CNT, if desired. This affects only the first period; subsequent timer periods always reset TMRn_CNT = 0x0000 0001.
7. Write the compare value to TMRn_CMP.
8. Set TMRn_CN.ten = 1 to enable the timer.
12.11 Capture/Compare Mode (7)
In capture/compare mode, the timer starts counting after the first external timer input transition occurs. The transition, a rising edge or falling edge on the timer's input signal, is set using the TMRn_CN.tpol bit.
After the first transition of the timer input signal, each subsequent transition captures the TMRn_CNT value, writing it to the TMRn_PWM register (capture event). When a capture event occurs, a timer interrupt is generated, the TMRn_CNT value is reset to 0x0000 0001, and the timer resumes counting.
If no capture event occurs, the timer counts up to the TMRn_CMP value. At the end of the cycle, where the TMRn_CNT equals the TMRn_CMP value, a timer interrupt is generated, the TMRn_CNT value is reset to 0x0000 0001, and the timer resumes counting.
Maxim Integrated Page 129 of 201 Figure 12-7: Capture/Compare Mode Diagram
β’β’β’
β’β’β’
TIMER CLOCK
SOFTWARE CLEARS .irq_clr
β’β’β’
β’β’β’
TMRn_CNT(CAPTURE)
β’β’β’
β’β’β’
Timer input signal triggers capture timer period event TMRn_CNT copied to TMRn_PWM β’β’β’
β’β’β’
0x0000_0000ο 0x0000_0001ο
TMRn_INTR.irq_clr TIMER INPUT
SIGNAL
0x0000_0002 TMRn_CNT
TMRn_CN.ten
TMRn_CN.tpol = 1 TMRn_CN.tpol = 0
TMRn_CMP
TMRn_CNT = TMRn_CMP Triggers rollover timer period
event
TMRn_PWM 0x0000_0000 TMRn_CNT(CAPTURE) SOFTWARE CLEARS 0x0000_0000 TMRn_PWM not affected by rollover
ο TMRn_CNT.count defaults to 0x0000_0000 on a timer reset. TMRn_CNT.count reloads to 0x0000_0001 for all following timer periods.
12.11.1 Capture/Compare Timer Period
The timer period ends when the selected transition occurs on the timer pin or on the clock cycle following TMRn_CNT = TMRn_CMP.
The timer peripheral automatically performs the following actions at the end of the timer period:
If a transition on the timer pin caused the end of the timer period:
1. The value in TMRn_CNT is copied to TMRn_PWM.
2. TMRn_CNT is reset to 0x0000 0001. The timer remains enabled and continues incrementing.
3. The timer interrupt bit, TMRn_INTR.irq_clr, is set.
a. An interrupt is generated if enabled.
If the end of the timer period is caused by transition on the timer pin:
1. TMRn_CNT is reset to 0x0000 0001. The timer remains enabled and continues incrementing.
2. The timer interrupt bit TMRn_INTR.irq_clr is set.
a. An interrupt is generated if enabled.
12.11.2 Capture/Compare Configuration
Configure the timer for capture/compare mode by performing the following steps:
1. Set TMRn_CN.ten = 0 to disable the timer.
2. Set TMRn_CN.tmode to 7 to select capture/compare mode.
3. Set TMRn_CN.pres3:TMRn_CN.pres to set the prescaler that determines the timer frequency.
4. Configure the timer pin:
a. Configure the pin as a timer input and configure the electrical characteristics as needed.
b. Set TMRn_CN.tpol to select the positive edge (TMRn_CN.tpol = 0) or negative edge (TMRn_CN.tpol = 0) transition causes the capture event.
5. If using the timer interrupt, enable the interrupt and set the interrupt priority.
6. Write an initial value to TMRn_CNT, if desired. This affects only the first period; subsequent timer periods always reset TMRn_CNT= 0x0000 0001.
7. Set TMRn_CN.ten to 1 to enable the timer. Counting starts after the first transition of the timer's input signal.
Note: No interrupt is generated by the first transition of the input signal.
In capture/compare mode, the elapsed time from the timer start to the capture event is calculated using Equation 12-11.