Master Mode Operation

The peripheral operates in master mode when master mode enable I2Cn_CTRL.mst = 1. To initiate a transfer, the master generates a START condition by setting I2Cn_MASTER_CTRL.start = 1. If the bus is busy, it does not generate a START condition until the bus is available.

A master can communicate with multiple slave devices without relinquishing the bus. Instead of generating a STOP condition after communicating with the first slave, the master generates a Repeated START condition, or RESTART, by setting I2Cn_MASTER_CTRL.restart = 1. If a transaction is in progress, the peripheral finishes the transaction before generating a RESTART. The peripheral then transmits the slave address stored in the transmit FIFO. The

I2Cn_MASTER_CTRL.restart bit is automatically cleared to 0 as soon as the master begins a RESTART condition.

I2Cn_MASTER_CTRL.start is automatically cleared to 0 after the master has completed a transaction and sent a STOP condition.

The master can also generate a STOP condition by setting I2Cn_MASTER_CTRL.stop = 1.

If both START and RESTART conditions are enabled at the same time, a START condition is generated first. Then, at the end of the first transaction, a RESTART condition is generated.

If both RESTART and STOP conditions are enabled at the same time, a STOP condition is not generated. Instead, a RESTART condition is generated. After the RESTART condition is generated, both bits are cleared.

If START, RESTART, and STOP are all enabled at the same time, a START condition is first generated. At the end of the first transaction, a RESTART condition is generated. The I2Cn_MASTER_CTRL.stop bit is cleared and ignored.

Maxim Integrated Page 145 of 201 A slave cannot generate START, RESTART, or STOP conditions. Therefore, when master mode is disabled, the

I2Cn_MASTER_CTRL.start, I2Cn_MASTER_CTRL.restart, and I2Cn_MASTER_CTRL.stop bits are all cleared to 0.

For master mode operation, the following registers should only be configured when either:

1. The I²C peripheral is disabled, or

2. The I²C bus is guaranteed to be idle/free.

If this peripheral is the only master on the bus, then changing the registers outside of a transaction (I2Cn_MASTER_CTRL.start = 0) satisfies this requirement:

• I2Cn_CTRL.mst_mode

• I2Cn_CTRL.rx_mode

• I2Cn_CTRL.scl_pp_mode

• I2Cn_CTRL.hs_mode

• I2Cn_RX_CTRL1.cnt

• I2Cn_MASTER_CTRL.sl_ex_addr

• I2Cn_MASTER_CTRL.master_code

• I2Cn_CLK_LO.lo

• I2Cn_CLK_HI.hi

• I2Cn_HS_CLK.hsclk_lo

• I2Cn_HS_CLK.hsclk_hi

In contrast to the above set of register fields, the register fields below can be safely (re)programmed at any time:

• All interrupt flags and interrupt enable bits

• I2Cn_TX_CTRL0.tx_thresh

• I2Cn_RX_CTRL0.rx_thresh

• I2Cn_TIMEOUT.scl_to_val

• I2Cn_DMA.rx_en

• I2Cn_DMA.tx_en

• I2Cn_FIFO.data

• I2Cn_MASTER_CTRL.start

• I2Cn_MASTER_CTRL.restart

• I2Cn_MASTER_CTRL.stop

14.4.6.1 I²C Master Mode Receiver Operation

When in master mode, initiating a master receiver operation begins with the following sequence:

1. Write the number of data bytes to receive to the I²C receive count field (I2Cn_RX_CTRL1.cnt).

2. Write the I²C slave address byte to the I2Cn_FIFO register with the R/W bit set to 1.

3. Send a START condition by setting I2Cn_MASTER_CTRL.start = 1.

4. The slave address is transmitted by the controller from the I2Cn_FIFO register.

5. The I²C controller receives an ACK from the slave and the controller sets the address ACK interrupt flag (I2Cn_INT_FL0.addr_ack = 1).

6. The I²C controller receives data from the slave and automatically ACKs each byte. The software must retrieve this data by reading the I2Cn_FIFO register.

7. Once I2Cn_RX_CTRL1.cnt data bytes have been received, the I²C controller sends a NACK to the slave and sets the Transfer Done Interrupt Status Flag (I2Cn_INT_FL0.done = 1).

8. If I2Cn_MASTER_CTRL.restart or I2Cn_MASTER_CTRL.stop is set, then the I²C controller sends a repeated START or STOP, respectively.

14.4.6.2 I²C Master Mode Transmitter Operation

When in master mode, initiating a master transmitter operation begins with the following sequence:

1. Write the I²C slave address byte to the I2Cn_FIFO register with the R/W bit set to 0.

2. Write the desired data bytes to the I2Cn_FIFO register, up to the size of the transmit FIFO. (e.g., If the transmit FIFO size is 8 bytes, the software can write one address byte and seven data bytes prior to starting the transaction.)

3. Send a START condition by setting I2Cn_MASTER_CTRL.start = 1.

4. The controller transmits the slave address byte written to the I2Cn_FIFO register.

5. The I²C controller receives an ACK from the slave and the controller sets the address ACK interrupt flag (I2Cn_INT_FL0.addr_ack = 1).

6. The I2Cn_FIFO register data bytes are transmitted on the SDA line.

a. The I²C controller receives an ACK from the slave after each data byte.

b. As the transfer proceeds, the software should refill the transmit FIFO by writing to the I2Cn_FIFO register as needed.

c. If the transmit FIFO goes empty during this process, the controller pauses at the beginning of the byte and waits for the software to either write more data or instruct the controller to send a RESTART or STOP condition.

7. Once the software writes all the desired bytes to the I2Cn_FIFO register, the software should set either I2Cn_MASTER_CTRL.restart or I2Cn_MASTER_CTRL.stop.

8. Once the controller sends all the remaining bytes and empties the transmit FIFO, it sets I2Cn_INT_FL0.done and proceeds to send out either a RESTART condition, if I2Cn_MASTER_CTRL.restart was set, or a STOP condition, if I2Cn_MASTER_CTRL.stop was set.

14.4.6.3 I²C Multi-Master Operation

The I²C protocol supports multiple masters on the same bus. When the bus is free, it is possible that two (or more) masters might try to initiate communication at the same time. This is a valid bus condition. If this occurs and the two masters want to transmit different data and/or address different slaves, only one master can remain in master mode and complete its transaction. The other master must back off transmission and wait until the bus is idle. This process by which the winning master is determined is called bus arbitration.

Maxim Integrated Page 147 of 201 To determine which master wins the arbitration, for each address or data bit, the master compares the data being

transmitted on SDA to the value observed on SDA. If a master attempts to transmit a 1 on SDA (that is, the master lets SDA float) but senses a 0 instead, then that master loses arbitration, and the other master that sent a zero continues with the transaction. The losing master cedes the bus by switching off its SDA and SCL drivers.

Note: This arbitration scheme works with any number of bus masters: if more than two masters begin transmitting simultaneously, the arbitration continues as each master cedes the bus until only one master remains transmitting. Data is not corrupted because as soon as each master realizes it has lost arbitration, it stops transmitting on SDA, leaving the following data bits sent on SDA intact.

If the I²C master peripheral detects it has lost arbitration, it stops generating SCL; sets the I2Cn_INT_FL0.arb_er field, sets I2Cn_INT_FL0.tx_lock_out field (flushing any remaining data in the transmit FIFO). The hardware also clears the

I2Cn_MASTER_CTRL.start, the I2Cn_MASTER_CTRL.restart, and the I2Cn_MASTER_CTRL.stop fields to 0. So long as the peripheral is not itself addressed by the winning master, the I²C peripheral stays in master mode (I2Cn_CTRL.mst = 1). If at any time another master addresses this peripheral using the address programmed in I2Cn_SLAVE_ADDR.addr, then the I²C peripheral clears the I2Cn_CTRL.mst field to 0 and begins responding as a slave. This can even occur during the same address transmission during which the peripheral lost arbitration.

Note: Arbitration loss is considered an error condition, and like the other error conditions sets I2Cn_INT_FL0.tx_lock_out.

Therefore, after an arbitration loss, the software needs to clear I2Cn_INT_FL0.tx_lock_out and reload the transmit FIFO.

Also, in a multi-master environment, the software does not need to wait for the bus to become free before attempting to start a transaction (writing 1 to I2Cn_MASTER_CTRL.start). If the bus is free when I2Cn_MASTER_CTRL.start is set to 1, the transaction begins immediately. If instead the bus is busy, then the peripheral:

1. Waits for the other master to complete the transaction(s) by sending a STOP, 2. Counts out the bus free time using 𝑡𝑡𝐵𝐵𝑈𝑈𝐹𝐹= 𝑡𝑡𝑆𝑆𝐺𝐺𝐿𝐿_𝐿𝐿𝑃𝑃 (see Equation 14-3), and then

3. Sends a START condition and begins transmitting the slave address byte(s) in the transmit FIFO, followed by the rest of the transfer.

The I²C master peripheral is compliant with all bus arbitration and clock synchronization requirements of the I²C specification; this operation is automatic, and no additional programming is required.