Core Operating Voltage Range Selection

The MAX32660 supports three selections for the core operating voltage range (OVR). In a single-supply operation, changing the OVR sets the internal LDO regulator's output to the voltage shown in Table 4-1. In a dual-supply design, setting the OVR allows an external PMIC to dynamically provide the required VCORE voltage. Changing the OVR also reduces the output frequency of the HFIO, further reducing power consumption.

Changes to the OVR affect the internal flash memory access time, and the application software must set the flash wait states for each OVR setting as outlined in the section Flash Wait States. Changing the core operating voltage reduces the output frequency of the HFIO immediately, as shown in Table 4-1. Operating the device using dual external supplies requires special considerations and must be handled carefully in software.

Changing the core operating voltage reduces the output frequency of the HFIO immediately, as shown in Table 4-1. When operating the MAX32660 using dual external supplies requires special considerations and must be handled carefully in the application software.

Table 4-1: OVR Selection and the Effect on VCORE and SYS_OSC PWRSEQ_LP_CTRL

ovr FLC_CN

lve VCORE Typical SYS_OSC

fHFIO

(MHz) fNANO

(kHz) fX32K

(kHz)

0 1 0.9 24 80 32.768

1 1 1.0 48 80 32.768

2 0 1.1 96 80 32.768

4.1.1 Setting the Operating Voltage Range

The OVR selection is controlled using the power sequencer low-power control register field PWRSEQ_LP_CTRL.ovr which is only reset by a power-on reset (POR). This field should be checked after every reset to determine the correct clock speed and flash wait states. Adjusting the OVR setting affects the frequency of the HFIO. Before adjusting the OVR settings, it is required to set the system clock to either the 80kHz NANO or the 32.768kHz external RTC oscillator. The device coordinates OVR change between the internal LDO and the HFIO set frequency. When changing the OVR setting, the device must be operating from the internal LDO. In a system using an external supply for VCORE, software must transition to the internal LDO before changing the OVR setting.

The following steps describe how to change the OVR for devices that use the HFIO as the default SYS_OSC:

1. Set PWRSEQ_LP_CTRL.ldo_dis to 0 to ensure the device is operating from the internal LDO for VCORE.

a. If using an external supply for VCORE, ensure the external supply is set to the same voltage as the current OVR setting. The external supply must be equal to or greater than the set OVR voltage.

2. Set either the 32.768kHz external RTC oscillator or the 80kHz NANO as the system clock source.

a. See the Oscillator Sources and Clock Switching section for details on the system clock selection.

Maxim Integrated Page 25 of 201 3. Set the number of flash wait states to 5 (GCR_MEMCKCN.fws = 5) to ensure flash operation at any frequency.

4. Set PWRSEQ_LP_CTRL.ovr to either 0, 1, or 2, as shown in Table 4-1.

5. Set FLC_CN.lve to either 0 or 1 according to the OVR setting set in step 4.

6. If desired, set the system clock source to the HFIO and update the system clock prescaler to the desired value.

a. Set GCR_CLKCN.clksel = 0.

b. Wait for the system clock ready bit, GCR_CLKCN.ckrdy, to read 1.

c. Set GCR_CLKCN.psc to the desired prescaler value.

7. Set GCR_MEMCKCN.fws to the minimum value shown for the selected system clock and OVR. See Table 4-2, Table 4-3, or Table 4-4 for details.

8. Set GCR_RSTR0.prst = 1 to perform a peripheral reset.

On each subsequent non-POR reset event:

1. Immediately after the reset event, set the flash low voltage enable bit to 1 (FLC_CN.lve = 1) to match the setting of the PWRSEQ_LP_CTRL.ovr field since the PWRSEQ_LP_CTRL.ovr field is not reset.

Note: Set the FLC_CN.lve to 1 in the reset vector code in RAM to ensure the low voltage enable is set before accessing any code in the flash memory.

2. Set the clock prescaler, GCR_CLKCN.psc, as needed by the system.

3. Set the number of flash wait states, GCR_MEMCKCN.fws, as needed based on the OVR setting using Table 4-2.

4.1.2 Flash Wait States

The setting for the number of flash wait states affects performance, and it is critical to set it correctly based on the PWRSEQ_LP_CTRL.ovr settings and SYS_CLK frequency. Set the number of flash wait states using the field

GCR_MEMCKCN.fws per Table 4-2. The GCR_MEMCKCN.fws field should always be set to the default POR reset value of 5 before changing the PWRSEQ_LP_CTRL.ovr settings. POR, system reset, and watchdog reset all reset the flash wait state field, GCR_MEMCKCN.fws, to the POR default setting of 5. When changing the system clock prescaler GCR_CLKCN.psc to move from a slower system clock frequency to a faster system clock frequency, always set GCR_MEMCKCN.fws to the minimum required for the faster system clock frequency before changing the system oscillator prescaler GCR_CLKCN.psc.

After a system reset or watchdog reset, the PWRSEQ_LP_CTRL.ovr setting overrides the default setting of the HFIO frequency to prevent system lockup. The FLC_CN.lve setting must be restored by software after any reset.

Important: Flash reads can fail and result in unknown instruction execution if the GCR_MEMCKCN.fws is lower than the minimum required for a given PWRSEQ_LP_CTRL.ovr setting and the selected system clock frequency.

Table 4-2: Minimum Flash Wait State Setting for Each OVR Setting (fSYSCLK = fHFIO) Core Operating Voltage Range Setting Core Voltage

Range fHFIO

(MHz) System Clock

Prescaler System Clock Minimum Flash Wait State Setting PWRSEQ_LP_CTRL.ovr FLC_CN.lve VCORE (V) GCR_CLKCN.psc fSYSCLK (MHz) GCR_MEMCKCN.fws

0 1 0.9 24 0 24 2

Core Operating Voltage Range Setting Core Voltage

Range fHFIO

(MHz) System Clock

Prescaler System Clock Minimum Flash Wait State Setting PWRSEQ_LP_CTRL.ovr FLC_CN.lve VCORE (V) GCR_CLKCN.psc fSYSCLK (MHz) GCR_MEMCKCN.fws

1 1 1.0 48 0 48 3

Table 4-3: Minimum Flash Wait State Setting for Each OVR Setting (fSYSCLK = fNANO) Core Operating Voltage Range Setting Core Voltage

Range

Table 4-4: Minimum Flash Wait State Setting for Each OVR Setting (fSYSCLK = fX32K) Core Operating Voltage Range Setting Core Voltage

Range

Maxim Integrated Page 27 of 201 Core Operating Voltage Range Setting Core Voltage

Range