11. Real-Time Clock (RTC)
11.7 RTC Registers
See Table 3-1 for the base address of this peripheral/module. If multiple instances of the peripheral are provided, each instance has its own independent set of the registers shown in Table 11-4. Register names for a specific instance are defined by replacing "n" with the instance number. For example, a register PERIPHERALn_CTRL resolves to
PERIPHERAL0_CTRL and PERIPHERAL1_CTRL for instances 0 and 1, respectively.
See Table 1-1 for an explanation of the read and write access of each field. Unless specified otherwise, all fields are reset on a system reset, soft reset, POR, and the peripheral-specific resets.
Table 11-4: RTC Register Summary
Offset Register Description
[0x0000] RTC_SEC RTC Seconds Counter Register [0x0004] RTC_SSEC RTC Sub-Second Counter Register [0x0008] RTC_RAS RTC Time-of-Day Alarm Register [0x000C] RTC_RSSA RTC Sub-Second Alarm Register [0x0010] RTC_CTRL RTC Control Register
[0x0014] RTC_TRIM RTC Trim Register
[0x0018] RTC_OSCCTRL RTC 32kHz Oscillator Control Register
11.7.1 Register Details
Table 11-5: RTC Seconds Counter Register
RTC Seconds Counter RTC_SEC [0x0000]
Bits Field Access Reset Description
31:0 sec R/W 0 Seconds Counter
This register is a binary count of seconds.
Table 11-6: RTC Sub-Second Counter Register
RTC Sub-Seconds Counter RTC_SSEC [0x0004]
Bits Field Access Reset Description
31:12 - RO 0 Reserved
11:8 - RO 0 Sec-Seconds Counter (Bits 11:8)
This field is not readable by software.
7:0 rtss R/W 0 Sub-Seconds Counter (Bits 7:0)
The lower 8 bits of this counter are located in this 8-bit field. The upper four bits of the sub-seconds counter, bits 11:8, are not readable by software.
The RTC_SEC register increments when the 12-bit sub-second counter field rolls from 0xFFF to 0.
Table 11-7: RTC Time-of-Day Alarm Register
RTC Time-of-Day Alarm RTC_RAS [0x0008]
Bits Field Access Reset Description
31:20 - RO 0 Reserved
19:0 ras R/W 0 Time-of-Day Alarm
This field sets the time-of-day alarm from 1 second up to 12 days. When this field matches RTC_SEC[19:0], an RTC system interrupt is generated.
Table 11-8: RTC Sub-Second Alarm Register
RTC Sub-Second Alarm RTC_RSSA [0x000C]
Bits Field Access Reset Description
31:0 rssa R/W 0 Sub-second Alarm
Sets the starting and reload value of the internal sub-second alarm counter. The internal counter increments and generates an alarm when the internal counter rolls from 0xFFFF FFFF to 0x0000 0000.
Table 11-9: RTC Control Register
RTC Control Register RTC_CTRL [0x0010]
Bits Field Access Reset Description
31:16 - RO 0 Reserved
15 we R/W 0* Write Enable
This field controls access to the RTC enable (RTC_CTRL.rtce_en) field.
0: Writes to the RTC_CTRL.rtce_en field are ignored.
1: Writes to the RTC_CTRL.rtce_en field are allowed.
*Note: Reset on system reset, soft reset, and the peripheral specific reset (GCR_RSTR0.rtc =1).
14:13 - RO 0 Reserved
12:11 x32kmd R/W 0 32KHz Oscillator Mode
0: Noise immune mode 1: Quiet mode
2: Quiet mode in low-power modes with warmup.
3: Quiet mode in low-power modes with no warmup.
10:9 ft R/W 0 Frequency Output Select
This field selects the RTC-derived frequency to output on the square wave output pin.
See Square Wave Output for configuration details.
0b00: 1.024Hz (Compensated) 0b01: 512Hz (Compensated) 0b1x: 4.096kHz
8 sqe R/W 0 Square Wave Output Enable
This field enables the square wave output. See Square Wave Output for configuration details.
0: Disabled 1: Enabled
7 alsf R/W 0 Sub-second Alarm Interrupt Flag
This interrupt flag is set when a sub-second alarm condition occurs. This flag is a wakeup source for the processor.
0: No sub-second alarm interrupt pending.
1: Sub-second alarm interrupt pending.
6 aldf R/W 0 Time-of-Day Alarm Interrupt Flag
This interrupt flag is set by hardware when a time-of-day alarm occurs.
0: No Time-of-Day alarm interrupt pending.
1: Time-of-day interrupt pending.
5 rdye R/W 0* RTC Ready Interrupt Enable
0: Disabled 1: Enabled
*Note: Reset on system reset, soft reset, and the peripheral specific reset (GCR_RSTR0.rtc =1).
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RTC Control Register RTC_CTRL [0x0010]
Bits Field Access Reset Description
4 rdy R/WO 0* RTC Ready
This bit is set to 1 for 120µs by hardware once a hardware update of theRTC_SEC and RTC_SSEC registers. Software should read RTC_SEC and RTC_SSEC while this hardware bit is set to 1. The software can clear this bit at any time. An RTC interrupt is
generated if RTC_CTRL.rdye = 1.
0: Software reads of RTC_SEC and RTC_SSEC are invalid.
1: Software reads of RTC_SEC and RTC_SSEC are valid.
*Note: Reset on System Reset, Soft Reset, and the peripheral specific reset (GCR_RSTR0.rtc =1).
3 busy RO 0* RTC Busy Flag
This bit is set to 1 by hardware to indicate a register update is in progress when the software writes to:
The field is automatically cleared by hardware when the update is complete. The software should poll this field for 0 after changing RTC registers or fields listed above before making any other RTC register changes.
0: Normal operation.
1: RTC busy.
*Note: Reset on POR only.
2 ase R/W 0* Sub-Second Alarm Interrupt Enable
Check the RTC_CTRL.busy flag after writing to this field to determine when the RTC synchronization is complete.
0: Disabled 1: Enabled
*Note: Reset on POR only.
1 ade R/W 0* Time-of-Day Alarm Interrupt Enable
Check the RTC_CTRL.busy flag after writing to this field to determine when the RTC synchronization is complete.
0: Disabled 1: Enabled
*Note: Reset on POR only.
0 rtce R/W 0* Real-Time Clock Enable
This field enables the RTC. The RTC write enable (RTC_CTRL.we) bit must be set to 1, and the RTC busy (RTC_CTRL.busy) field must read 0 before writing to this field. After writing to this bit, check the RTC_CTRL.busy flag for 0 to determine when the RTC synchronization is complete.
0: Disabled 1: Enabled
*Note: Reset on POR only.
Table 11-10: RTC Trim Register
RTC Trim RTC_TRIM [0x0018]
Bits Field Access Reset Description
31:8 vbattmr R/W 0 VRTC Time Counter
The hardware automatically increments this field every 32 seconds while the RTC is enabled.
Note: This field is only reset on a POR.
7:0 trim RTC Trim
This field specifies the 2's complement value of the trim resolution. Each increment or decrement of this field adds or subtracts 1ppm on each 4.096kHz clock value with a maximum correction of ± 127ppm.
Table 11-11: RTC 32kHz Oscillator Control Register
RTC 32kHz Oscillator Control RTC_OSCCTRL [0x0018]
Bits Field Access Reset Description
31:6 - R/W 0 Reserved
5 out32k R/W 0 RTC Square Wave Output
0: Disabled
1: Enables the 32kHz oscillator output or the external clock source output on the square wave output pin. See Square Wave Output for configuration details.
*Note: Reset on POR only.
4 bypass R/W 0 RTC Crystal Bypass
This field disables the RTC oscillator and allows an external clock source to be driven on the 32KIN pin.
0: Disable bypass. RTC time base is an external 32kHz crystal.
1: Enable bypass. RTC time base is an external square wave (driven on the 32KIN input pin).
*Note: Reset on POR only.
3 ibias_en RO 1 Reserved
2 hyst_en RO 0 Reserved
1 ibias_sel RO 0 Reserved
0 filter_en RO 1 Reserved
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