performance of the well-known VAX-1 1/780 system, for the three new VAX 4000 systems, respectively. The CPU cycle clock speed and cache sizes deter mine the product performance, as d iscussed in the section CPU-cache Subsystem.
The backplane in the system e nclosure provides the signal in terconnection and power d istribution between system components. There are connec tors and slots for the CPU module, four slots for MS690 memory modules, and seven Q-bus slots. The CPU module has a 270-pin connector that receives the module power and connects the CPU to the NVAX memory interconnect (NMI) bus, the system DSSJ bus, and the Q-bus. The backplane was m odified to support tile wider 72-bit clata path of the new MS690 memory modu les. This new back plane was phased into the BA440, enabling most VAX 4000 Model 300 systems to be upgraclecl with out requiring a backplane change.
The system enclosure supports up to fou r DSSI or small computer system interface (SCSI) tape inte grated storage elements (ISEs). These cableless bricks support either one 5.25 -inch, ful l-height drive or two 3.5 -inch drives. The ISEs are available i n variants that support the 2-gigabyte (GB), RF73 DSSI disk drive and dual 85MB, RF35 DSSI d isk drives. The single-system pedestal can support six RF35 devices and a tape drive, providing 4.8GB of storage for appl ications that requ ire h igh I/O rates. This RF35 configuration can provide over 360 queued 1/0s per second for random 1/0s. If RF73 drives are used, the single-system box can provide 8GB of storage. There are several ways to expand the base VAJ(
4000 system; the most common way is to expand to another DSSI-based system ancl create a two- or three-node DSSI VAXcluster. The Q-bus in the V�'< 4000 system can be expanded to provide 10 addi tional Q-bus slots to each system using the B213A Q-bus expansion enclosure. The DSSI expansion enclosures together with the Q-bus DSST adapter (KFQSA) can expand the total available cl isk storage to 28 DSSI disks. Using the RF73 disk allows up to 56GB of d isk storage.
CPU Module
The CPU moclule common to the three new VAX 4000 systems is based on a highly integrated CPU ancl l!O system built on the single 21 .6-by-26.7- centimeter (8.5-by-10.5-inch) m odule shown in
NV AX-microprocessor VAX Systems
Figures 2 and 3. The CPU moclu le print eel wmng board (PWB) consists of the fol lowing subsystems: a cen tral processor and its associated three-level cache; a pin bus, bus adapter, and memory control ler; and an 1/0 system with integrated control. lers for DSSI and Ethernet buses. The CPU module also con tains a CQBIC and 512KB of field erasable program mable read-only memory (FEPROM) for console code.
CPU-cache Subsystem
The CPU-cache subsystem is built around the single chip NVAX CPU, which p rovides a three-level cache architecture. The first two levels of cache, which are contained on the chip, i nclude a 2KB virtually addressed instruction cache and an 8KB physically addressed i nstruction a nd data cache. The thircl level of cache, the backup cache, is constructed using static random-access memories (SRAMs) on the module ancl is completely controlled by the NVAX CPU chip. The backup cache was designed to support a CPU cycle t ime as low as 10 nanoseconds
NDAL-TO-CP BUS ADAPTER CHIP (NCA)
(ns) with a slip cycle, i . e . , a two-cycle read (20 ns) using 8 -ns SRAMs. This write-back caching architec ture significantly reduces the demands on main memory by caching both reads and writes without the need for a memory access. On all previous VAX 4000 systems, the caches required that a l l write operations continue through to main memory, i.e., write through.
The NVAX is clocked by a differential emitter coupled logic (ECL) surface acoustic wave oscilla tor. This oscil lator runs at 250 megahertz (MHz) (16 -ns cycle time), 286 MHZ (14-ns cycle time), or 333 MHz (12-ns cycle time) on the KA675, K.A680, and KA690 CPU modules, respectively. The NVAX chip produces a four-phase i nternal clock directly from this input and generates system c locks at one third the internal clock rate.
The new CPU module design supports either a 128-kilobyte (KB) or a 512KB backup cache. (512KB for the KA690 module and 128KB for the K.A680 and KA675.) The tag store for the two cache sizes can be
SGEC ETH E R N ET ADAPTER C H I P S H A G DSSI ADAPTER C H I P NVAX MEMORY CONTROLLER (NMC) CVAX 0-BUS INTERFACE C H I P (CQBIC) SHAG DSSI ADAPTER C H I P
Figure 2 CPU Module
Design of the VAX 4000 Model 400, 500, and 600 Systems
ETH E R N ET DSSI BUS
SGEC SHAG DSSI ETH ERNET ADAPTER ADAPTER CHIP OR 5 1 2KB CHIP B-CACHE SRAMS N DAL-TO-CP CP BUS 1
NVAX BUS ADAPTER
CHIP (NCA) CPU SYSTEM FPU SUPPORT P-CACHE (\J CHIP (SSC) B-CACHE NVAX (/)