The MS690 fam i ly of CNIOS memory modules was designed to support the memory req uirements set fo rth by the f'NA)( memory controller. 2 The NMC
requires the MS690 memory module to provide a two-way, bank-interleaved , 72-bit data path . In add i tion, a self test feature is provided that was used on the V�'<: 4000 Model 300 memory su bsystem. The MS690 module returns a u nique board ident ifica tion signature when polled by the NMC. The mod ule used existing qua lified parts and fits on a quad-sized PWB.
A common goal of Digital's Electronic Storage Devel opment (ESD) teams is to uti l ize a single PWB design to accom modate as many memory sizes as possible. The ESD teams ro utinely stretch the boundaries of Digital's manufacturing processes to provide world-class memory su bsystems. Because memory subsystems form the core of the ESD char ter, the ESD teams are uniquely tuned into, and actively shaping, present and future device speci fi cations for aU types of random-access devices. This advance and i ntimate knowledge al lows us to build current technology products with the hooks neces sary to capital ize on the next generation of storage devices.
The MS690 options are available in 32 MB, 64MB, and 128MB sizes and are selfconfiguring. The MS690 memories comm un icate with the NMC by way of the private NMI. AJJ control and clocks sig nals originate off-board via the NMI from the NMC. Up to tour memory modules of a ny densi ty mix may coexist on the NMI with a m aximum memory size of 512MB
The MS690 is an ex tension of the existing 39-bit MS670 memory product designee! fo r the VA)\. 4000
Model 300 product line. The DC562 GMX was designed and produced i n D igital's Hudson, achuset ts, plant for the MS670 32MB mem ory. This
Design
of
the VAX 4000 Mode/ 400, 500, and 600 SystemsGMX is a semi-inte l l igent, 20-bit-wide, 4- to-1 and 1- to-4 transceiver, with internal test/compare/error logging capabilities for its five l/0 ports. The MS670 required eight banks of 39 bits of data, hence the requ irement of two GMX chips per module.
The KA670 CPU module used in the VA.,'{ 4000 Model 300 transfers 32-bit longwords of data. For every longword , 7 bits of ECC must be a l located, i.e. , 8 x (32 + 7)
== 312 DRAivls. The CPU modu le used in the VAX 4000 Model 500 transfers 64-bit quad words of data. For every quadword, 8 bits of ECC must be al located, i.e. , 4 x (64 + 8) == 288 DRAMs. The MS690 memory is configured as two i nter leaved bank pairs, each 72 bits wide (64 bits of data plus 8 bits of ECC); all transactions are 72 bits. The memory module supports quadword, octaword, and he.l(word read/write/read-modify-write trans actions. Transactions less than 72 bi ts, i.e., bytes, words, and long words, are not supported.
Doubling the data word length is advantageous in two ways: the l/0 bandwidth effectively dou bles, and 24 fewer DRAMs are requ ired. This last benefit resu I ts from the fact that only one additional bit is required to protect 64 bits of data as compared to protecting 32-bit data. The ava ilable PWB space al lowed room fo r two additional GMXs to handle the 33 additional data bits. The abi l ity to use the existing GMX integrated circuit eliminated the need for a new, 40-bit-wide, <�MX-type VLSI development.
Because DRAMs are edge-sensitive devices, mod u le layout, bala nced etch transm ission I ines, and signal cond itioning are extremely important to a quality product. The MS690 design team used a combined total of 18 years of memory design experience al ong with exten sive use of SPICE modeling to determine the optimal P\VB layout. The result was a double-sided, su rface-mount P\X-13 panel that can accommodate all density variations
of the MS690 memory option and thus help control costs by reducing product-u nique inventory. Al l parts, except the bare PCB, are used on products a l ready produced in volume at Digital 's Singapore and Ga lway, I reland, manufacturing plants.
The MS690-BA memory module, which uses lOO ns 1 M-by-1 M D RAMs, can support NMC cycle ti mes of 36 ns and 42 ns, respectively, for the VAX 4000 Model 400 and 500 systems. The MS690-CA/DA mod u les use 80-ns 4M-by-1 M DRAMS and can accom modate 30-ns, 36 -ns, and 42-ns NMC cycle times.
Performance
The CPU 1/0 subsystems on a l l three products pro vide exceptiona l performance, as shown in Table 3. The pair of DSSI buses on the CPU modu les for the VAX 4000 Models 500 and 600 were tested under the VMS operating system performing si ngle-block (512-byte) reads from RF73 disk drives. The read rate was measu red at over 2,600 1/0s per second with both buses ru nning. The Ethernet subsystem, based on the SGEC adapter ch ip, is al so very effi cient. It has been measured transmitting and receiv i ng 192-byte- long packets at a rate of 5,882 packets
per second. Packets 1 ,581 bytes long can be trans mitted at a rate of 9.9 megabits per second.
The performance of the CPU su bsystem has tradi tiona l ly been measu red using a su i te of 99 bench marks 7 Sca ling the resu lts against the performance of the VAX-1 1/780 processor and taking the geo metric mean y ields the VAX unit of performance
(YUP)
rating. The processor VUP rating for the new VAX 4000 system with the lowest performance, the Model 400, is twice the VUP rating of the sys tem it is replacing, the Model 300. The two new high-end systems provide three and four times the performance of the Model 300-an impressive per formance increase.Table
3
Summary of Performa nce Resu lts for the VAX 4000 Models 400, 500, and 6007Metric Unit
SPEC Release 1 .0 SPECmark
SPECint SPECfp
Si ngle User 99 VUPs
TPC-A tpsA-Iocal Dhrystone I nteger M I PS Whetstone Single M I PS Whetstone Double M I PS LI NPACKD (1 00 by 1 00) MFLOPS UNPACKS M FLOPS
Digital Tee/mica/ jourual Vnl. 4 No. 3 Summer 1991
Model 400 Model 500 Model 600
22.3 30.7 41 .1 1 7.1 24.9 31 .8 26.6 35.4 48.7 1 6.9 23.8 31 . 4 51 .0 62.4 1 03.0 34.2 43.4 64.4 47.6 71 .4 83.3 32.3 45.5 52.6 4.8 6.9 9.5 7.5 1 0.5 1 4.7 71
NV AX-microprocessor VAX Systems
The system performance in multistream and transaction-oriented environments was measured with TPC Benchmark A H This benchmark, which
simulates a banking system, genera lly ind icates per formance in environments that are characterized by concurrent CPU a nd l/0 activity and that have more than one program active at any given time. The per formance metric is transacti o ns per seco nd (TPS). The measu red performance of the VAX 4000 Model 600 system was more than 100 TPS, tpsA-local. As shown in Table 3. the performance of the new VA.'{ 4000 Model 400, 500, and 600 systems is impres sive, even compared to RJSC-based systems.