The function of the row drive circuits of an active matrix LC display is to select each row electrode in turn as the corresponding video data is applied to the columns of the display by the column drive circuit. The row drive circuit operates at the line frequency of the video signal and is therefore relatively undemanding of transistor performance.
The selection of successive rows is normally performed by a static shift register as shown in Figure 5-7. A bi-directional shift register is often used allowing the scan direction o f the display to be reversed. Outputs are usually taken from both master and slave sections of the shift register as this reduces the number of shift register sections required. A consequence of this is that successive shift register output pulses overlap by half the clock period. Non overlapping pulses are required to address the rows of the display and one method of generating these is to use NAND gates as shown in Figure 5-7. The shift register is normally designed using minimum size transistors. Therefore a chain of inverters of increasing size is needed to drive the relatively large row capacitance of the display.^"^ Mohsen 1979] ^ j^ u r n ^ g r o f
shift register designs which have been used in row and column drive circuits are described in section 5.4.6.
Clock /Clock Carry
Shift Register
Outputs to Display Rows
Figure 5-7 Row drive circuit using a shift register
An alternative to the use of a shift register for selecting the rows of a display is an address bus and decoders^^ as shown in Figure 5-8. An advantage of this arrangement is that it does not rely on the propagation of a signal through a TFT circuit to select the successive outputs. A defect in a shift register is likely to prevent all succeeding stages from addressing the display correctly. With the decoder arrangement a defect in one of the
decoders, once isolated, is unlikely to affect other parts of the circuit making this design more tolerant of defects. A disadvantage of a drive circuit based on decoders is the area required to accommodate the address bus lines and the relatively complex decoder logic. For example a VGA resolution display with 480 rows would require a 9-bit address bus and 9-bit decoding logic. This approach for generating scanning signals has not been widely used.
Address Bus
Decoder
1
Î
(
Row
Figure 5-8 Row drive circuit using a decoder
In some TFT row and column drive circuit designs level shifting stages are introduced between the shift register or decoder and the output stages of the circuit.^ i9 9 4 ][ y Nishihara 1992] output section of the circuits must be operated at the relatively high voltages
required to address the display but by introducing level shifters the shift registers or decoders can be operated at a lower voltage. There are a number of circumstances where it may be necessary to consider the use of level shifters. Takaftiji^^ Takafuji 1993] it necessary to use
dual gate transistors in the output stages of the circuits because of the relatively high bias voltages. Introducing level shifters between the output circuits and the shift registers allows single gate transistors to be used in the remainder of the circuit. Higashi^^ Higashi 1995]
use of level shifters to overcome a problem encountered with improving TFT performance. It was found that as the operating voltage of a shift register was increased, the sensitivity of the circuit to mistiming of the complementary clock signals, clock skew, also increased. Reducing the power supply voltage of the shift registers resulted in more reliable circuit operation and reduced power consumption. These advantages have to be balanced against the additional complexity of the level shifting circuits and the increased propagation delays which result from operating the circuits at lower power supply voltages.
Determining the size of the transistors in the inverters which form the output of the row drive circuit is an important aspect of the circuit design. These transistors must charge and discharge the row capacitance with acceptable rise and fall times. The equation below, which is derived in appendix A, can be used to estimate the 10%-90% or 90%-10% transition times o f the signal at the output o f a CMOS inverter.
1
log
O.IF. - 1
5-1
where C is the load capacitance, V D D is the power supply voltage, V j is the transistor threshold voltage, B = and = —
L tax
Rearranging this equation results in the transistor width required to achieve a certain transition time.
W = C L 1 log
O.IF,DD
5-2
Substituting values for the various parameters, power supply voltage To/)=16V, mobility
j U p = 8 0 c m ^ /V s //„=100cm^A^s, threshold voltage V j p ^ - S W V j^ „ = 5 V , gate capacitance Co;t=2.3xlO'^F/m^, gate length Zp=6pm and T„=6pm.
0 8 4 ^
P rp
^ 1 0 % - 9 0 %
5-3
y - 0 6 7 7C _ 5-4
Considering the charging of the pixels, it is important that the pixel TFTs are turned off before the voltages on the columns start to change to the new values required for the next row of pixels. A typical value for the 90%-10% fall time would be 2ps, which ensures that the pixel TFTs can be turned off within the line blanking period o f the video signal. To achieve this value of fall time the n-channel device in the output inverter should have a width of approximately 34pm for each lOOpF of load capacitance. The rise time o f the row select pulses is less critical than the fall time and it is often convenient to make the width of the p- channel device the same as the n-channel transistor.
The row capacitance of displays o f different resolutions and sizes has been estimated in appendix B and the results are illustrated in Figure 5-9. It is assumed in these calculations that the pixel storage capacitors are connected to the adjacent row electrodes. As the display size increases the row capacitance also increases and therefore larger transistors are required in the output section of the row drive circuit. There is not an absolute limit on size of transistors which can be used in the drive circuits, but as their size increases the drive circuits will have a greater effect on the yield of the display. While considering what is a practical size for the output TFTs of integrated drive circuits S. Tomita^^ Tomita i996] size
of the transistors to the pitch o f the pixels in the display. An alternative approach which is more closely related to the effect of circuits on display yield is to compare the active area of the transistors in the output section of the drive circuit with the active area o f the transistors used within the pixels of the display.
10000 1000
8
CL 8I
100 — VGA - . SVGA 0 2 4 6 8 10 12 14 16 18 20Display diagonal (inches)
Figure 5-9 Row capacitance o f displays with different resolutions and diagonals
If it is assumed that the total gate area of p-channel or n-channel output transistors should represent no more than 5% of the gate area o f the pixel transistors then it is possible to calculate the maximum display size which satisfies this requirement. The results are summarised in Table 5-1 for colour datagraphic displays of three different resolutions. The results indicate that high resolution displays can be made at larger sizes than lower resolution displays. This simply reflects the fact that the display size limit has been based on the
relative area o f the pixel and circuit TFTs. The higher resolution displays have a greater number o f pixel transistors and therefore wider transistors can be used within the row drive circuit. In practice lower resolution displays would also be made at the larger sizes but the impact on display yield would be slightly greater. This result shows that in terms of the size o f the output TFTs, it is quite practical to consider integrating the row drive circuits of displays up to 18-inches diagonal.
Display Resolution VGA SVGA XGA
Columns x Rows (640x3)x480 (800x3)x600 (1024x3)x768
Total width o f pixel transistors (m) 3.7 5.8 9.4
Maximum output TFT width (fim) 193 484 612
Maximum display diagonal (inches) 10 15 18
Table 5-1 Maximum display size based on width of row driver output transistors
10000 1000 Q. 8 CL 5 100
row o s c a p a c ito r electro d e s e p a r a te c a p a c ito r electro d e
8 10 16
0 2 4 6 12 14 18 20