6.5 Pixel Charging Time
6.5.2 Multilevel Column Data
An N-bit conversion using two level input data requires N input data charging and charge sharing cycles to complete the conversion. This number can be reduced if the number of discrete voltage levels applied to the input of the converter is increased. Two possible schemes for reducing the number of charging cycles are presented here. In the first scheme, simultaneous bit conversion, the additional input voltage levels allow two or more bits of the digital data to be converted simultaneously. In the second scheme, the output voltage range of the converter is divided into a number of smaller intervals which are selected according to the most significant bits of the data.
Consider first the simultaneous bit conversion approach. In general if 2^ input voltage levels are used and there are N conversion cycles then the overall conversion resolution is MxN. Consider an example where an overall conversion with a resolution of 8-bits is needed. The possible combinations for the number of input voltage levels and the number of charging cycles is given in Table 6-5. The conversion could be achieved by carrying out an eight bit serial conversion using two level input data and requiring eight data charging periods. Alternatively the number of charging cycles could be reduced to 4 if four level input data were used in a simultaneous bit conversion scheme. The relative values of the input voltage levels required when two, four, eight and sixteen separate data levels are used are
summarised in Table 6-6. The values needed depend on the number o f conversion cycles, N, of the serial digital to analogue conversion. The way in which the digital video data is used to select one of the column voltage levels for conversions where four or sixteen column data levels are used is illustrated schematically in Figure 6-18 for the case o f eight bit video data.
Column Voltage Levels Data Charging Cycles
2* = 256 1
^ = 1 6 2
f = 4 4
2 ^ = 2 8
Table 6-5 Combinations o f column levels and charging cycles for an 8-bit conversion
2-level data 4-level data 8-level data 16-level data 1 1 +2'^ 1 + 2‘^ + 2'2N 1+ 2'^ + 2'^^ + 2'^^ 1 + 2'^ 4- 2'^^ 1 + 2 ^ 1 + 2’^ + 2'^^ 1 + 2 ^ 1 1 + 2'^^ 1 2' ^ + 2'^^ 1 + 2'^ ^ 1 1 +2'^^ 1 0 2 -n 2'N ^ 2 ‘2N 2 ' N 2 ’2n + 2 ’3n 2 ' N 2*2n 2 -n 2 -n _ ^ 2 ‘ 3n 2 -n 0 2-2N 2 '2n + 2'3N 2 " 2 N 0 2 - 3 N 0
Table 6-6 Values o f multilevel digital data for an N-bit simultaneous bit conversion schem e
With four level column signals the upper and lower four bits of the 8-bit video data are effectively processed in parallel with corresponding bit pairs being used to select the column voltage. For example the least significant bits, Bg and B], are used to select the first column voltage level of the conversion. In the second period B^ and B2 control the column voltage in the third B? and B3 and the fourth Bg and B4.
8-bit parallel video data 8-bit parallel video data
MSB LSB
select one of four reference voltages
4-bit 4-level serial data
MSB LSB
select one of sixteen reference voltages
2-bit 16-level serial data
Figure 6-18 Selection of multilevel column data for simultaneous bit conversion
A similar method is used to select the appropriate data voltage when sixteen voltage levels are used, but in this case two groups of four data digits are used to select one of the sixteen voltage levels as shown in Figure 6-18. A circuit arrangement for implementation of the conversion using four bit four level data is illustrated on the left of Figure 6-19. The number of conversion cycles is reduced by a factor of two at the cost of doubling the number of voltage selection switches and introducing a 2 to 4 line decoder to control the switches.
M x N - b i t p a r a l l e l d a t a p a r a l l e l d a t a m s b s h i f t
f i
Isb d i r e c t i o n M M t o 2 decoder - C o l u m n s i g n a l P ix e l serial 0/À converter N cydes m s b s h i f t d i r e c t i o n Mnto^ +1 ^ decoding logic r- 2 C o l u m n s i g n a l P ix e l serial D/A converter.. N cydes _ Isb S i m u l t a n e o u s B it C o n v e r t i o n ( M = 2 N = 4 M x N = 8 ) D i v i d e d R a n g e C o n v e r t e r ( M = 2 N = 6 M + N = 8 )In the second approach to reducing the number of cycles required to perform a conversion the output voltage range is divided into a number o f separate intervals, 2, 4, 8 or 16, which are defined by a set of reference voltages. This technique is sometimes used with conventional digital to analogue converters in order to increase their output voltage resolution. The circuit requirements o f this scheme are illustrated on the right o f Figure 6- 19. In the divided range conversion the most significant bits o f the digital data are used to select a pair o f reference voltage levels. One of these two levels is then applied to the input o f the converter according to the state of the less significant bits o f the data. As the most significant bits of the data are used to select the output voltage range, the number of bits used in the serial data conversion is reduced. If the output voltage range is divided into 2^ intervals and the serial digital to analogue conversion has a resolution o f N bits, then the overall conversion resolution is M+N bits. For example, to perform a conversion with an overall resolution of 8 bits a serial conversion of the 6 least significant bits o f the data could be performed with the 2 most significant bits of the data being used to select one of four output voltage ranges.
Compared to the simultaneous bit conversion scheme, the divided range approach does not provide as great a reduction in the number of charging cycles of the serial converter. In the example shown in Figure 6-19 the number o f cycles is reduced from 8 to 6 for the divided range approach compared to a reduction from 8 to 4 for the simultaneous conversion. Dividing the output voltage range of the converter in this way does, however, offer the possibility of generating a non-linear output voltage which can be matched to some extent to the characteristics of the liquid crystal.