Multiplexer Control Circuit Design

The groups o f multiplexer switches within the column drive circuit are controlled by one or more shift registers as indicated in Figure 5-30. By using a number of shift registers operating with clock signals having different phases the clock frequency o f each individual shift register can be reduced.

« S’ ct £ s ■E I 3

Figure 5-30 Combinations of shift registers and video lines

Many different designs for CMOS shift registers exist. A number of designs which have been applied to the row and column drive circuits for AMLC displays are described here. Two basic CMOS static shift register circuits which provide scanning in a single direction are shown in Figure 5-31. The first circuit uses inverters and transmission gates^^ Nishiham and requires eight TFTs per section. The second design replaces the transmission gates with clocked inverters and requires ten TFTs per s e c tio n .M a e k a w a I992] [ h o h s h im a 1993] [ t

c c — [>^-i — — t » T c 1

Figure 5-31 Shift registers for single scan direction

C1 C1 C1 C2 C2 [H Asada 1996] R C C R R — < K ]— — 4 0 - C R [T Maekawa 1994]

-40

Figure 5-32 Shift registers for bi-directional scanning

Examples of shift registers which are capable of bi-directional scanning are shown in Figure 5-32. The circuit used by A sada^ is similar to the previous circuit which used clocked inverters, but in this arrangement the carry signal from one section to the next is passed via a transmission gate rather than an inverter so that it can pass in either direction. The scan direction is determined by the relative phase o f the two clock signals. If Cl and C2 are in phase then the carry signal is shifted from right to left. If C l and C2 are complementary then the signal is shifted from left to right. The number of TFTs used is only eight per section

The bi-directional circuit adopted by Maekawa ^ also uses transmission gates to route the carry signal from one section to the next. If the direction control signal R is high then the signal passes from left to right, if it is low the signal is passed from right to left. The circuit uses sixteen TFTs per section and is combined with a method for reducing clock line loading which is described below. The shift register used by Takafuji ^

is made up entirely from clocked inverters with sixteen transistors per section. The scan direction is controlled by complementary direction control signals which enable inverters passing the shift register signal from left to right if R is high and enable inverters passing the signal from right to left if R is low. There is no clear choice as to which shift register circuit is best. Although some circuits require a larger number o f transistors these devices will generally be small and therefore the increase is unlikely to have a large effect on the yield or layout o f the circuit.

CLK

CLK

lo ca l C lo c k lin e s C lo c k b u s lin e s

U Maekawa 1994]

As the size and resolution o f displays increases, greater demands are placed on the performance o f the shift registers. One problem is the increased load capacitance on the clock lines o f the shift register as the number o f register sections increases. A technique for reducing the clock line loading described by Maekawa Maekawa 1994] gj^Qwn in Figure 5-33. In this circuit the clock signals used within each section o f the shift register are isolated from the clock bus lines by two transmission gates. These transmission gates are normally turned off but when a high level appears at the input to the shift register section the transmission gates are turned on and the clock signals are passed to the clocked inverters. The transmission gates remain turned on until the output o f the register section goes low. When the transmission gates are turned off the signal C is held low and its complement held high by high resistance load devices. The advantage o f this circuit is that the input capacitance of the transmission gates when they are turned off is lower than the capacitance of the clock inputs o f the clocked inverters. As a result the capacitive loading of the clock bus lines is reduced.

Another issue for the design o f high performance shift register circuits is the effects of clock skew. Hashizume Hashizume 1994] a shift register circuit in which a single clock line is distributed to the shift register sections and local complementary clocks are generated for each section as shown in Figure 5-34.

C lo c k B u s L ine L ocal C o m p le m e n ta ry C lo c k s C1 C1 C 2 C 2 C1 C 2 [T H a s h iz u m e 19 9 4 ]

Figure 5-34 Shift register with locally generated com plementary clocks

The timing of the operation of the multiplexer switches is an important aspect of the operation of the drive circuit. Two issues which must be considered are illustrated in Figure 5-35. The first is the timing of the operation of the multiplexer switches relative to the changing video information applied to the video lines.

*pd ^

Video data periods ' " X ,

Switch group n

Switch group n+1

‘o,

Figure 5-35 M ultiplexer switch timing

There will be a propagation delay, tpj, between the external control signals applied to the column drive circuit and the operation of the multiplexer switches. If this delay is not taken into account then the transmission gates would switch off after the voltages on the video lines had been changed to the levels required for the next group of columns in the display. The visual effect of this would be the presence of a double image on the display, the horizontal separation of the images corresponding to the width of one group of multiplexer switches. If the propagation delay is similar for all the multiplexer switch groups within the drive circuit then it can be compensated for by adjusting the phase o f the video data relative to the column driver control signals. If the propagation delay is large compared to the video data periods or if it varies with the position in the drive circuit, for example due to clock skew, then it may not be possible to select a satisfactory clock phase for all parts of the circuit. In this case the number of video lines would have to be increased so that the video data periods could be extended.

A second potential source of error in the operation of the multiplexer is overlapping o f the switching signals as indicated by toi i" Figure 5-35. The effect of this overlap is shown in an exaggerated form in Figure 5-36. The video bus line is represented by an RC transmission line. When the second multiplexer switch turns on the current which flows through the video line to charge the column capacitance causes the voltage at the first switch to fall, partially discharging the first column. If the first switch turns off before this

disturbance to the video bus voltage has settled then an incorrect voltage will be sampled onto the first column. This problem can be avoided by ensuring that the gate drive signals o f switches which are connected to the same video line are non-overlapping.

Video Bus Line

S2 S1