Row Drive Circuit

The row drive circuit is illustrated in Figure 5-40. It consists of a shift register, NAND gates to control the timing of the row select pulses, level shifters and output drivers. Level shifters are used to allow the output voltages to be adjusted independently of the power supply voltage of the shift register.

shift register CLK CLK CLK C LK /CLK /CLK /CLK /CLK /O W N /O W N /OW N /O W N OW N O W N OWN OW N 0 E 2 0 E 1

pulse width control

level shift

output driver

Figure 5-40 Schematic diagram of row drive circuit

The bi-directional shift registers consist of two inverters and four transmission gates for each section. The scan direction is determined by the levels applied to the complementary scan direction control signals DWN and /DWN. A high level signal DWN turns on the transmission gate which passes the output of the shift register section to the right while a low level causes the output signal to be passed to the left. The width of all TFTs in the shift register is 10pm, the n-channel transistors used in the inverters have LDD at the drain end of the channel while those in the transmission gates have LDD at both ends o f the channel.

The output pulses produced by the shift register overlap by half the clock period. In order to generate the non-overlapping pulses required to address the rows of the display the shift register signals pass through NAND gates which mask the pulses with externally generated output enable signals OEl and OE2.

A diagram illustrating the row drive circuit in more detail is shown in Figure 5-41. Two stages of level shifting have been used to isolate both the high and low level output voltages from the power supply voltage used by the shift register. In the first level shifter the high level of the signal from the shift register is changed from VDD to the output voltage level VDDO and in the second the low voltage level is altered from VSS to VSSO. All o f the control signals for the row drive circuit are at the levels of VDD and VSS. Two inverters are used at the output of the second level shifter to drive the row capacitance o f the display.

To next section / C L K O W N V D D 10/6 10/6 10/6 10/6 10/6 10/6 C L K /D W N 10/6 10/6 10/6 10/6 10/6 10/6 V S S / C L K D W N To next section O E V D D O V D D V S 10/6 10/6 15/6 15/6 5/18 15/6 120/6 -O _5/18 10/6 10/6 10/6 15/6 15/6 5/18 5/18 _{15/6 120/6} 10/6 V M S V S S V S S O

Figure 5-41 One section o f row drive circuit

The width of the output transistors was chosen to give rise and fall times o f less than 2ps for a full 6-inch display. Separate power supply levels, VS and VNS, were supplied to the output inverter in order to allow the output voltage to be modulated if part o f the drive voltage for the LC was applied via the common electrode o f the display. Modulation of VNS would result in reversal of the drain source voltage across the n-channel device in the output

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inverter. In order to prevent this causing hot carrier degradation LDD was incorporated at both ends o f the channel of this transistor.

The layout o f the row drive circuit is shown in Figure 5-42. Autom ated layout of TFT circuits is not yet established and therefore the transistors and circuits were built up by defining polygons in the various mask layers used during the fabrication o f the displays. The main constraint on the layout is that the pitch of the outputs o f the circuit must match the pitch o f the rows in the display, 190.5jJ.m. The large transistors which form the output inverter can be seen at the bottom o f the picture and the shift register at the top. A second shift register was included in the layout, connected in parallel with the first, in order to provide a degree o f redundancy. Defects in one of the registers can be isolated using laser cutting allowing the second register to function correctly. Probe pads are connected to nodes within the shift register and at the row drive outputs for use during inspection of the circuit. The total height o f the circuit is 1400pm.

Figure 5-42 Layout of row drive circuit