Enhanced secure digital host controller (eSDHC)

This section describes the DC and AC electrical specifications for the eSDHC interface.

3.15.1 eSDHC DC electrical characteristics

This table provides the DC electrical characteristics for the eSDHC interface.

Table 82. eSDHC interface DC electrical characteristics (dual-voltage cards)

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Characteristic Symbol Condition Min Max Unit Notes

Input high voltage VIH - 0.7 x VDD - V 1

Input low voltage V_IL - - 0.2 x V_DD V 1

Input/Output leakage current I_IN/I_OZ - -50 50 μA

-Output high voltage V_OH I_OH = -100 μA at V_DD min

V_DD - 0.2 V - V

-Output low voltage V_OL I_OL= 100 μA at V_DD min

- 0.2 V

-Output high voltage V_OH I_OH = -100 μA V_DD - 0.2 - V 2

Output low voltage V_OL I_OL = 2 mA - 0.3 V 2

1. The min V_IL and V_IH values are based on the respective min and max V_IN values found in Table 3.

2. Open-drain mode is for MMC cards only.

3. For recommended operating conditions, see Table 3.

4. SDHC interface is powered by EV_DD and CV_DD. The V_DD and V_IN in the table above should be replaced by the respective IO power supply.

3.15.2 eSDHC AC timing specifications

This table provides the eSDHC AC timing specifications as defined in Figure 45 and Figure 46 (EV _DD /CV _DD = 1.8V or 3.3V).

Table 83. eSDHC AC timing specifications (High Speed/Full Speed)

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Parameter Symbol¹ Min Max Unit Notes

SDHC_CLK clock frequency SD/SDIO (full-speed/high-speed

mode) f_SCK 0 25/50 MHz 2, 4

MMC full-speed/high-speed mode 20/52

SDHC_CLK clock low time (full-speed/high-speed mode) t_SCKL 10/7 — ns 4 SDHC_CLK clock high time (full-speed/high-speed mode) t_SCKH 10/7 — ns 4

SDHC_CLK clock rise and fall times t_SCKR/

t_SCKF

— 3 ns 4

Input setup times: SDHC_CMD, SDHC_DATx to SDHC_CLK t_NIIVKH 2.5 — ns 3, 4, 5 Input hold times: SDHC_CMD, SDHC_DATx to SDHC_CLK t_NIIXKH 2.5 — ns 4, 5 Output hold time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid t_NIKHOX -3 — ns 4, 5 Output delay time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid t_NIKHOV — 3 ns 4, 5 Notes:

Table 83. eSDHC AC timing specifications (High Speed/Full Speed)

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Parameter Symbol¹ Min Max Unit Notes

1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state)

for inputs and (first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, t_FHSKHOV symbolizes eSDHC high-speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. In full-speed mode, the clock frequency value can be 0-25 MHz for an SD/SDIO card and 0-20 MHz for an MMC card. In high-speed mode, the clock frequency value can be 0-50 MHz for an SD/SDIO card and 0-52 MHz for an MMC card.

3. To satisfy setup timing, one-way board-routing delay between Host and Card, on SDHC_CLK, SDHC_CMD, and

SDHC_DATx should not exceed 1 ns for any high speed MMC card. For any high speed or default speed mode SD card, the one way board routing delay between Host and Card, on SDHC_CLK, SDHC_CMD, and SDHC_DATx should not exceed 1.5ns.

4. C_CARD ≤ 10 pF, (1 card), and C_L = C_BUS + C_HOST + C_CARD ≤ 40 pF.

5. The parameter values apply to both full-speed and high-speed modes.

6. For recommended operating conditions, see Table 3.

This figure provides the eSDHC clock input timing diagram.

eSDHC external clock

VM VM VM

tSCK

t_SCKL t_SCKH

t_SCKR t_SCKF VM = Midpoint voltage (OV_DD/2)

Figure 45. eSDHC clock input timing diagram

This figure provides the data and command input/output timing diagram.

SDHC_CLK external clock

VM VM VM

t

NIIXKH

SDHC_DAT/CMD inputs

SDHC_DAT/CMD outputs

VM t

NIIVKH

t

^NIKHOV

VM = Midpoint voltage (OV

DD

/2) t

^NIKHOX

Figure 46. eSDHC data and command input/output timing diagram referenced to clock

This table provides the eSDHC AC timing specifications for SDR50 mode (EV _DD /CV _DD

= 1.8V).

Table 84. eSDHC AC timing (SDR50)

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Parameter Symbol Min Max Unit Notes

SDHC_CLK clock frequency: f_SCK 100 MHz

SDHC_CLK duty cycle 47 53 %

SDHC_CLK clock rise and fall times t_SCKR/

t_SCKF

- 2 ns 1

Skew between SDHC_CLK_SYNC_OUT and SDHC_CLK — -0.1 0.1 ns —

Input setup times: SDHC_CMD, SDHC_DATx to SDHC_CLK_SYNC_IN

t_NIIVKH 2.1 - ns

Input hold times: SDHC_CMD, SDHC_DATx to SDHC_CLK_SYNC_IN

t_NIIXKH 0.9 - ns

Output hold time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid,

SDHC_DATx_DIR, SDHC_CMD_DIR t_NIKHOX 2.4 - ns

Output delay time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid,

SDHC_DATx_DIR, SDHC_CMD_DIR tNIKHOV - 6.3 ns

Notes:

1. C_CARD ≤ 10 pF, (1 card), and C_L = C_BUS + C_HOST + C_CARD ≤ 30 pF.

2. For recommended operating conditions, see Table 3.

This figure provides the eSDHC clock input timing diagram for SDR50 mode.

eSDHC external clock

VM VM VM

t_SCK

tSCKR tSCKF

VM = Midpoint voltage (EV_DD/2)

Figure 47. eSDHC SDR50 mode clock input timing diagram

This figure shows the eSDHC input AC timing diagram for SDR50 mode.

SDHC_CLK_SYNC_IN

SDHC_CMD/

SDHC_DAT input

TCLK

TNIIVKH TNIIXKH

Figure 48. eSDHC SDR50 mode input AC timing diagram

This figure shows the eSDHC output AC timing diagram for SDR50 mode.

SDHC_CMD/SDHC_CMD_DIR

Figure 49. eSDHC SDR50 mode output AC timing diagram

This table provides the eSDHC AC timing specifications for DDR50/eMMC DDR mode (EV _DD /CV _DD = 1.8V).

Table 85. eSDHC AC timing (DDR50/eMMC DDR)

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Parameter Symbol Min Max Units Notes

SDHC_CLK clock frequency SD/SDIO DDR50 mode f_SCK — 50 MHz —

eMMC DDR mode 50

SDHC_CLK duty cycle — 47 53 % —

Skew between SDHC_CLK_SYNC_OUT and SDHC_CLK — -0.1 0.1 ns —

SDHC_CLK clock rise and fall times

SD/SDIO DDR50 mode t_SCKR/ t_SCKF

— 4 ns 1

eMMC DDR mode 2 2

Input setup times: SDHC_DATx to SDHC_CLK_SYNC_IN

SD/SDIO DDR50 mode t_NDIVKH 0.5 — ns —

eMMC DDR mode 0.6

Input hold times: SDHC_DATx to

SDHC_CLK_SYNC_IN SD/SDIO DDR50 mode tNDIXKH 0.98 — ns —

eMMC DDR mode 0.98

Output hold time: SDHC_CLK to SDHC_DATx valid,

SDHC_DATx_DIR

SD/SDIO DDR50 mode t_NDKHOX 2.2 — ns —

eMMC DDR mode 3.9

Output delay time: SDHC_CLK to SDHC_DATx valid,

SDHC_DATx_DIR

SD/SDIO DDR50 mode t_NDKHOV — 5.7 ns —

eMMC DDR mode 6.3

Input setup times: SDHC_CMD to

SDHC_CLK_SYNC_IN SD/SDIO DDR50 mode tNIIVKH 3.3 — ns —

eMMC DDR mode 2.7

Input hold times: SDHC_CMD to SDHC_CLK_SYNC_IN

SD/SDIO DDR50 mode t_NIIXKH 0.4 — ns —

eMMC DDR mode 0.4

Output hold time: SDHC_CLK to SDHC_CMD valid,

SDHC_CMD_DIR

SD/SDIO DDR50 mode tNIKHOX 2.2 — ns —

eMMC DDR mode 4.4

Table continues on the next page...

Table 85. eSDHC AC timing (DDR50/eMMC DDR)

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(continued)

Parameter Symbol Min Max Units Notes

Output delay time: SDHC_CLK to SDHC_CMD valid,

SDHC_CMD_DIR

SD/SDIO DDR50 mode t_NIKHOV — 12.2 ns —

eMMC DDR mode 14.6

Notes:

1. C_CARD ≤ 10 pF, (1 card).

2. C_L = C_BUS + C_HOST + C_CARD ≤ 20 pF for MMC. 40pF for SD.

3. For recommended operating conditions, see Table 3.

This table provides the eSDHC AC timing specifications for eMMC DDR mode (EV _DD /CV _DD = 3.3V).

Table 86. eSDHC AC timing (eMMC DDR)

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Parameter Symbol Min Max Units Notes

SDHC_CLK clock frequency eMMC DDR mode f_SCK — 49 MHz —

SDHC_CLK duty cycle — 47 53 % —

Skew between SDHC_CLK_SYNC_OUT and SDHC_CLK — -0.1 0.1 ns —

SDHC_CLK clock rise and fall

times eMMC DDR mode tSCKR/

t_SCKF

— 2 ns 2

Input setup times: SDHC_DATx to SDHC_CLK_SYNC_IN

eMMC DDR mode t_NDIVKH 1.33 — ns —

Input hold times: SDHC_DATx to SDHC_CLK_SYNC_IN

eMMC DDR mode t_NDIXKH 1.32 — ns 4

Output hold time: SDHC_CLK to SDHC_DATx valid,

SDHC_DATx_DIR

eMMC DDR mode t_NDKHOX 3.9 — ns —

Output delay time: SDHC_CLK to SDHC_DATx valid,

SDHC_DATx_DIR

eMMC DDR mode t_NDKHOV — 6.3 ns —

Input setup times: SDHC_CMD to SDHC_CLK_SYNC_IN

eMMC DDR mode t_NIIVKH 2.7 — ns —

Input hold times: SDHC_CMD to SDHC_CLK_SYNC_IN

eMMC DDR mode t_NIIXKH 0.4 — ns —

Output hold time: SDHC_CLK to SDHC_CMD valid,

SDHC_CMD_DIR

eMMC DDR mode t_NIKHOX 4.4 — ns —

Output delay time: SDHC_CLK to SDHC_CMD valid,

3. For recommended operating conditions, see Table 3.

4. Refer eSDHC A-008936

This figure shows the eSDHC DDR50/eMMC DDR mode input AC timing diagram.

SDHC_CLK_SYNC_IN

SDHC_DAT input

SDHC_CMD input

TCLK

TNDIVKH T NDIXKH

TNIIVKH TNIIXKH

Figure 50. eSDHC DDR50/DDR mode input AC timing diagram

This figure shows the DDR50/eMMC DDR mode output AC timing diagram.

SDHC_CLK

SDHC_DAT/

SDHC_DATn_DIR output

SDHC_CMD/

SD_CMD_DIR output

TCLK

TNDKHOV

TNDKHOX

TNIKHOV

TNIKHOX

Figure 51. eSDHC DDR50/DDR mode output AC timing diagram

This table provides the eSDHC AC timing specifications for SDR104/eMMC HS200 mode as defined in Figure 52 (EV _DD /CV _DD = 1.8V).

Table 87. eSDHC AC timing (SDR104/eMMC HS200)

Parameter Symbol Min Max Units Notes

SDHC_CLK clock frequency SD/SDIO SDR104 mode f_SCK — 165 MHz —

eMMC HS200 mode 175

SDHC_CLK duty cycle — 47 53 % —

SDHC_CLK clock rise and fall times t_SCKR/

t_SCKF

— 1 ns 1

Output hold time: SDHC_CLK to SDHC_CMD, SDHC DATx valid, SDHC_CMD_DIR,

SDHC_DATx_DIR

SD/SDIO SDR104 mode t_NIKHOX 1.58 — ns —

eMMC HS200 mode 1.6

Output delay time: SDHC_CLK to SDHC_CMD, SDHC DATx valid, SDHC_CMD_DIR,

SDHC_DATx_DIR

SD/SDIO SDR104 t_NIKHOV — 4.15 ns —

eMMC HS200 mode 3.9

Input data window (UI) SD/SDIO SDR104 mode t_IDV 0.5 — Unit

interval

—

eMMC HS200 mode 0.475

Notes:

1. C_L = C_BUS + C_HOST + C_CARD ≤ 10 pF.

2. For recommended operating conditions, see Table 3.

This figure provides the SDR104/HS200 mode timing diagram.

SDHC_CLK

SDHC_CMD/

SDHC_DAT input

SDHC_CMD/SDHC_CMD_DIR SDHC_DAT/SDHC_DATn_DIR

output DATA DATA

DATA

T_NIKHOX

T_NIKHOV

T_IDV Tclk

Figure 52. SDR104/eMMC HS200 mode timing diagram

In document T1040. Freescale Semiconductor. Data Sheet: Technical Data Rev. 2, 06/2015. Document Number T1040 (Page 115-124)