QUICC Engine Specifications

3.12.1 HDLC, Transparent, and Synchronous UART interfaces

This section describes the DC and AC electrical specifications for the high level data link control HDLC, transparent and synchronous UART.

3.12.1.1 HDLC, Transparent and Synchronous UART DC electrical characteristics

This table provides the DC electrical characteristics for the HDLC, Transparent and Synchronous UART protocols.

Table 64. HDLC, Transparent and Synchronous UART DC electrical characteristics (DVDD=3.3V)

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Parameter Symbol Min Max Unit Notes

Input high voltage V_IH 0.7 * DVDD - V 1

Input low voltage V_IL - 0.2 * DVDD V 1

Input current (V_IN = 0 V or V_IN = DV_DD) I_IN - ±50 μA 2

Output high voltage (DVDD = min, IOH = -2 mA) VOH 2.4 - V

-Output low voltage (DV_DD = min, I_OH = 2 mA) V_OL - 0.4 V

-1. The min V_IL and max V_IH values are based on the respective min and max DV_IN values found in Table 3

2. The symbol VIN, in this case, represents the input voltage of the supply. It is referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

This table provides the DC electrical characteristics for the HDLC, Transparent and Synchronous UART protocols.

Table 65. HDLC, Transparent and Synchronous UART DC electrical characteristics (DVDD=2.5V)

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Parameter Symbol Min Max Unit Notes

Input high voltage V_IH 0.7 * DVDD - V 1

Input low voltage VIL - 0.2 * DVDD V 1

Input current (V_IN = 0 V or V_IN = DV_DD) I_IN - ±50 μA 2

Output high voltage (DV_DD = min, I_OH = -1 mA) V_OH 2.0 - V

-Output low voltage (DV_DD = min, I_OH = 1 mA) V_OL - 0.4 V

-1. The min VIL and max VIH values are based on the respective min and max DVIN values found in Table 3

Table 65. HDLC, Transparent and Synchronous UART DC electrical characteristics (DVDD=2.5V)

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Parameter Symbol Min Max Unit Notes

2. The symbol V_IN, in this case, represents the input voltage of the supply. It is referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

3.12.1.2 HDLC, Transparent and Synchronous UART AC timing specifications

This table provides the input and output AC timing specifications for HDLC, and Transparent and Synchronous UART protocols.

Table 66. HDLC, Transparent AC timing specifications

Parameter Symbol Min Max Unit Notes

Outputs-Internal clock delay t_HIKHOV 0 5.5 ns 1

Outputs-External clock delay t_HEKHOV 1 8.5 ns 1

Outputs-Internal clock High Impedance t_HIKHOX 0 5.5 ns 1

Outputs-External clock High Impedance t_HEKHOX 1 8.2 ns 1

Inputs-Internal clock input setup time t_HIIVKH 8.0 - ns

-Inputs-External clock input setup time t_HEIVKH 4 - ns

-Inputs-Internal clock input Hold time t_HIIXKH 0 - ns

-Inputs-External clock input hold time t_HEIXKH 1 - ns

-Notes:

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin.

2. For recommended operating conditions, see Table 3.

3. The Maximum frequency of operation is 50MHz

This table provides the input and output AC timing specifications for the synchronous UART protocols.

Table 67. Synchronous UART AC timing specifications

Parameter Symbol Min Max Unit Notes

Outputs-Internal clock delay t_HIKHOV 0 11 ns 1

Outputs-External clock delay t_HEKHOV 1 14 ns 1

Outputs-Internal clock High Impedance t_HIKHOX 0 11 ns 1

Outputs-External clock High Impedance tHEKHOX 1 14 ns 1

Inputs-Internal clock input setup time t_HIIVKH 10 - ns

-Inputs-External clock input setup time t_HEIVKH 8 - ns

-Table continues on the next page...

Table 67. Synchronous UART AC timing specifications (continued)

Parameter Symbol Min Max Unit Notes

Inputs-Internal clock input Hold time t_HIIXKH 0 - ns

-Inputs-External clock input hold time t_HEIXKH 1 - ns

-Notes:

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin.

2. For recommended operating conditions, see Table 3.

This figure provides the AC test load.

Output DV_{DD /2}

RL = 50 Z0= 50 Ʊ

Ʊ

Figure 29. AC test load

These figures represent the AC timing from Table 66 and Table 67. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. This figure shows the timing with external clock.

Serial CLK (input)

Input Signals:

(See Note)

Output Signals:

(See Note)

Note: The clock edge is selectable

t HEIVKH t HEIXKH

t HEKHOV

t HEKHOX

Figure 30. AC timing (external clock) diagram

This figure shows the timing with internal clock.

Serial CLK (output)

Input Signals:

(See Note)

Output Signals:

(See Note)

Note: The clock edge is selectable

t HIIVKH t HIIXKH

t HIKHOV

t HIKHOX

Figure 31. AC timing (internal clock) diagram

3.12.2 TDM/SI

This section describes the DC and AC electrical specifications for the time-division-multiplexed and serial interface (TDM/SI).

3.12.2.1 TDM/SI DC electrical characteristics

This table provides the TDM/SI DC electrical characteristics.

Table 68. TDM/SI DC electrical characteristics (DVDD=3.3V)

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Parameter Symbol Min Max Unit Notes

Input high voltage V_IH 0.7 * DVDD - V 1

Input low voltage V_IL - 0.2 * DVDD V 1

Input current (V_IN = 0 V or V_IN = DV_DD) I_IN - ±50 μA 2

Output high voltage (DV_DD = min, I_OH = -2 mA) V_OH 2.4 - V

-Output low voltage (DV_DD = min, I_OH = 2 mA) V_OL - 0.4 V

-1. The min V_IL and max V_IH values are based on the respective min and max DV_IN values found in Table 3

2. The symbol V_IN, in this case, represents the input voltage of the supply. It is referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

Table 69. TDM/SI DC electrical characteristics (DVDD=2.5V)

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Parameter Symbol Min Max Unit Notes

Input high voltage V_IH 0.7 * DVDD - V 1

Input low voltage V_IL - 0.2 * DVDD V 1

Input current (V_IN = 0 V or V_IN = DV_DD) I_IN - ±50 μA 2

Table continues on the next page...

Table 69. TDM/SI DC electrical characteristics (DVDD=2.5V)

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(continued)

Parameter Symbol Min Max Unit Notes

Output high voltage (DV_DD = min, I_OH = -1 mA) V_OH 2.0 - V

-Output low voltage (DV_DD = min, I_OH = 1 mA) V_OL - 0.4 V

-1. The min V_IL and max V_IH values are based on the respective min and max DV_IN values found in Table 3

2. The symbol V_IN, in this case, represents the input voltage of the supply. It is referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

3.12.2.2 TDM/SI AC timing specifications

This table provides the TDM/SI input and output AC timing specifications.

Table 70. TDM/SI AC timing specifications

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Parameter Symbol ¹ Min Max Unit

TDM/SI outputs-External clock delay t_SEKHOV 2 11 ns

TDM/SI outputs-External clock High Impedance t_SEKHOX 2 10 ns

TDM/SI inputs-External clock input setup time t_SEIVKH 5 - ns

TDM/SI inputs-External clock input hold time t_SEIXKH 2 - ns

Notes:

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin.

2. For recommended operating conditions, see Table 3.

NOTE

The rise/fall time on QUICC Engine block input pins should not exceed 5 ns. This should be enforced especially on clock signals. Rise time refers to signal transitions from 10% to 90%

of DV _DD ; fall time refers to transitions from 90% to 10% of DV _DD

This figure provides the AC test load for the TDM/SI.

Output DV_{DD /2}

RL = 50 Z0= 50 Ʊ

Ʊ

Figure 32. TDM/SI AC test load

This figure represents the AC timing from Table 70. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. This figure shows the TDM/SI timing with external clock.

tSEKHOX Note: The clock edge is selectable on TDM/SI

Output Signals:

TDM/SI (See Note) Input Signals:

TDM/SI (See Note) TDM/SICLK (input)

t SEIVKH tSEIXKH

tSEKHOV

Figure 33. TDM/SI AC timing (external clock) diagram

In document T1040. Freescale Semiconductor. Data Sheet: Technical Data Rev. 2, 06/2015. Document Number T1040 (Page 101-106)